DAC37J84: FIFO empry error flag

Cafain,

Data sheet(SLASE17B) page96
　bit1 = read_error : Asserted if read request with empty FIFO
　bit0 = read_empty : FIFO is empty

Q1.
Please explain the meaning of bit0 and bit1 (difference between both).

If bit0 is set to "1", an error occurred. This error is indicating the FIFO is empty, which should never occur in normal operating mode.

If bit1 is set to "1", an error occurred when the device was reading the FIFO and it was empty. Both of these errors are related.

As a result of confirmation by evaluation, bit0="0" and bit="1" are set.
When FIFO is in empty state, it is thought that bit1="1" because read was executed,
If FIFO is in empty state, we think that bit0="1".

However, bit0="0" and bit1="1" are confirmed.
We think that bit0="1" and bit1="1" when FIFO is empty, is it wrong?

How did you confirm the FIFO was empty?
　
Q2.
bit1 = read_error : Asserted if read request with empty FIFO

In which phase of the JESD204B interface is the phase in which bit1 error occurs?
Is it code group synchronization (CGS), or initial lane synchronization (ILAS),
or will it occur in the data transmission phase?

Since data is not valid until after ILAS, the user should clear the alarms after this stage before monitoring.

Regards,

Jim

Hi, Jim-san

answer

A1.

Please contact us if there is a shortage with the following information.

· Initialization of FPGA and DAC37J84 respectively
· Supplies SYSREF to both
• 0x64, 0x65 register cleared to zero, then read → When the read result is 0x0002 (bit 1 is set to "1")

Additional Information
Things found out in the recent evaluation
The RF output was confirmed by setting 0x03 bit7 fifo_error_zeros_data_ena to "0"
from the above state (bit 1 is set to "1").

I am using K = 32, but is it the correct answer?

A2.

FPGA is XC7Z100, XC7K325T.
SYNC has confirmed that it is outputting from DAC37J84, and the data transmission phase is
I think that it is reachable.

best regards

Cafain

Hi, Jim-san
I appreciate your support for it as the question gets more.

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>> A2.
>> Since data is not valid until after ILAS, the user should clear the alarms after this stage before monitoring.

⇒ I will confirm with the above A2 answer.
　 Is it correct that the way to clear alarm is zero write clearing of 0x64 and 0x65?
   Please let me know otherwise if necessary

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In addition, let me ask you a question in addition.
The DAC3XJ8X-GUI tool has the following description.
(Please see the red line of the attached file for the description location)

"IF "FIFO Read Error" or "FIFO Read Empty" is observed,
  　Reset the JESD core and trigger SYSREF again.

The operation method of "Reset the JESD core"
Set [0x4A bit 0 jesd_reset_n] from '1' (reset released state) to '0' (reset state)
Is it correct in the procedure to turn it back to '1' again?

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best regards

HI, Jim san

I'm sorry to issue lots of questions and get confused.

I want to know,
It is how Bit 0 = "0", Bit 1 = "1" of config100 (0x64), config101 (0x65) is set in what state.

If the FIFO is empty, Bit 0 is "1" and since I read the empty state, I think that Bit 1 = "1".

The actual value is Bit 0 = "0" and Bit 1 = "1" when FIFO is called.

Is the difference when Bit 1 is "0" and when it is "1" related to Bit 0?

best regards

cafain

Hello jim-san

I am waiting for your answer.
Please take action on this matter.

If there is missing information, please request me.

best regards

cafain

Cafain,

When the last word is read from the FIFO, bit 0 gets set to a "1" indicating to the user that the FIFO is now empty. This is a warning, not an error. If this FIFO gets read again without loading, bit 1 gets set to a "1" indicating to the user that this was a bad read as the FIFO was empty and a read occurred.

Config100 corresponds to lane 0 and Config101 corresponds to lane 1. 

Regards,

Jim