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ADC32RF45: Understanding data rates corresponding to decimation settings..

Amanda Ross95
Intellectual 2740 points
Part Number: ADC32RF45

Hello there,

I have a customer who reached out to me with a question regarding the on-chip tuners internal to the ADC32RF45 (DDC Block) and they're looking to understand the correlation between the multiple data rates (output from device over JESD links) and different decimation settings as they're developing the DSP code in their FPGA.

He is planning to use the device in receiver mode while using two bands. Please see his question below--

'In looking at the datasheet for the device, I see that table 3 on p.34 describes output rates and bandwidths based on the sample rate for various decimation settings and it seems pretty straightforward. However, when I look at Figure 76 on p.35 which gives an example of a dual-band divide by 8 complex setting and try to reconcile the numbers shown in the figure with Table 3, things don't match.

The figure shows that the complex output data rate is 750MSPS per band for divide-by-8 and a sample rate of 3GSPS, while table 3 shows that the rate should be 375MSPS per band complex for the same sample rate. There is a factor of two discrepancy and I'm wondering if there is either a mistake in the figure or perhaps I am not understanding something (like does the rate in the figure refer to IQ pair rate, while the table refers to individual IQ stream rates which are presumably interleaved)?

Can you shed some light on this?'

Appreciate any feedback your team can offer us! Thank you for your time.

-Amanda

  • 0
    TI__Expert 3855 points

    Hi Amanda,

    looks like there is a typo in figure 76.

    With 3Gsps and complex /8 decimation the output rate should be 375Msps complex. Table 3 is correct. We'll get that updated in the data sheet.

    Best regards,

    Tommy

  • 0 in reply to Thomas Neu
    TI__Intellectual 2740 points
    Thank you for the quick response Thomas!
  • 0 in reply to Thomas Neu
    Prodigy 140 points

    Hi,

    Following up on this, can you clarify what "375Msps complex" means?

    Does this mean that a sample (I or Q) is output at 375Msps or is this actually the I/Q pair rate so one pair of I/Q samples comes out at 375Msps?

    Thanks!

    John

  • 0 in reply to John Dusatko
    TI__Mastermind 29220 points

    Hi,

    The data in the I stream is at 375Msps and the data in the Q stream is also at 375Msps.    The actual data format for the decimation by 8 complex mode of operation can be seen in tables 22 and 23 or tables 16 and 17 - depending on whether you want two DDC blocks enabled and depending on how many lanes you want to put the sample data out onto.    With dual band enabled, tables 22 and 23 show that the IQ data can be put out onto 4 lanes or 8 lanes.    With single band enabled tables 16 and 17 show that the IQ data can be put out onto 4 lanes or 2 lanes.   And in each case you can see which samples are formatted onto which lanes.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 140 points

    Richard,

    Thanks for getting back to me.

    OK, I’m still unclear and I think it relates to the actual data format coming out of the DDC blocks. My basic question relates to what will the data format and rate be when the I/Q data is turned back into parallel at the receiving end. I need to know this in order to process the data.
    So taking the example of dual band (two DDC blocks per ADC being used), complex by-8 decimation, sampling at 3000MSPS, with two lanes per ADC channel (4 lanes for the whole device), so LMFS = 4841, table 23 shows that essentially one serdes lane is wired to one DDC block, correct?
    Then coming out of one DDC block in this operating mode, how is the I/Q data formatted? 
    Is it:
    DDCn Out:   I0 Q0 I1 Q1 … In Qn in one parallel stream (so each sample is I or Q, interleaved) at 375MSPS
    -or- (and I think this is what is being said above):
    DDCn Stream 1      I0 I1 … In        at 375MSPS 
    DDCn Stream 2     Q0 Q1 … Qn  at 375MSPS
    So figure 76 would show two lines coming out of the LPF one for I, one for Q? If this is correct, then how is this data sent across the serdes lane? Following table23, its shown that the I/Q samples are interleaved, so there would be an interleaved parallel 16b I/Q data stream going into the serdes at 750MSPS. However, if I use the lane rate equation: 
    LR = (M * N’ * S * 10/8 * FC)/L
    With: M=8, N’=16, S=1, FC=750MSPS, L=4
    Then I get LR = 30Gbps, which makes no sense. Even if I use FC=375MSPS, then LR is halved to 15Gbps, which is still too large. So I’m hoping you can help clear up my confusion. So can you please 1) clairfy how the data comes out of the DDC and 2) How is the DDC output rate related to the JESD lane rate.
    Thanks and Regards,
    /John
  • 0 in reply to John Dusatko
    TI__Mastermind 29220 points

    Hi,

    Figure 76 is just saying that if you enable two DDCs per channel (dual band) then coming out of each DDC block is an I/Q pair, and the I stream is at 375Msps and the Q stream is at 375Msps.  (not 750M - that was simply a typo.)    This is what the data is after the DDC, before it is sent to the JESD204b block where it is mapped onto lanes according to the mode of operation chosen.     This is why the M value is 8 - there are two channels each with two DDCs, and each of the DDCs is outputting an I stream and a Q stream, so it looks to the FPGA downstream like you have 8 data converters running: M=8.

    In the case of the LMFS=4841 that you have pointed to, yes the data from each DDC block is routed to the coding and serializer for a single lane of the link.  In this case, one of the DDCs from channel A would go to lane DA1.  The other DDC from channel A would go to lane DA2. One of the DDCs from channel B would go to lane DB1. The other DDC from channel B would go to lane DB2.   And table 23 tells you that on each lane you get the most significant byte of the I sample first, then the least significant byte, then the most significant byte of the Q sample, then the least significant byte.  These four octets form the basic frame for this mode of operation.  F=4.   

    So the line rate *would* be 15Gbps on each lane with M=8 * N=16x1.25 * S=1 * 375Msps / 4.   And that is too fast for the max line rate that the RF45 can support.  In Table22 for the decimate by 8 LMFS=4841 case you can see in the very last column that the ratio of sample rate to JESD204b line rate is a ratio of 5, or 3Gsps time 5 = a lane rate of 15Gbps.   So the LMFS=4841 mode cannot support a sample rate of 3Gsps.  The max sample rate that could be supported by LMFS=4841 decimate by 8 would be 2.5Gsps so that 2.5Gsps x 5 = 12.5Gbps.     In this mode of operation, the max line rate of the serial lanes is what would limit the max sample rate of the device.   For a 3Gsps sample rate, you would have to use the LMFS=8821 mode to spread the data over 8 lanes rather than 4 to stay under the max lane rate limit.

    Regards,

    Richard P.