ADC12DJ3200EVM: Configuration GUI is not able to connect to the EVM

Hi Patrick

The information returned by FT_PROG indicates the ADC12DJ3200EVM you have is a preliminary revision sent to advance customers prior to release of the product.

My recommendation is you work with the TI personnel who provided that board to get one of the final production boards that will work with the EVM GUI software you have downloaded.

If you need to get going in the meantime I can provide a link to a different EVM GUI installer that will work with the board that you have.

Can you also let me know which TSW14J5x capture board model and revision you have?

Best regards,

Jim B

It would be great to get that installer, thanks!  The capture board is a TSW14J56 revision D.  

Hi Patrick

Here is the ADC12DJ3200EVM GUI installer for the board you have.

/cfs-file/__key/communityserver-discussions-components-files/73/3162.ADC12DJxx00EVM_5F00_GUI_5F00_Installer_5F00_S2P0_5B00_1_5D00_.zip

Can you confirm the ADC board is marked Revision E3?

You will need .ini files to enable use of this board with the TSW14J56EVM that you have. If you can tell me which JMODEs you want to use I will send appropriate .ini files.

Best regards,

Jim B

Hi Patrick

OK, good.

Here are .ini files to enable that E3 board with the TSW14J56 Rev D.

/cfs-file/__key/communityserver-discussions-components-files/73/8875.TSW14J56_5F00_Rev_5F00_D_5F00_INI_5F00_Files_5F00_for_5F00_ADC12DJxx00E3_5B00_1_5D00_.zip

Copy these files into the following folder location:

C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J56revD Details\ADC files

And here is the quick start guide created to support that revision of ADC EVM:

/cfs-file/__key/communityserver-discussions-components-files/73/4382.ADC12DJxx00EVM_5F00_E2_5F00_E3_5F00_Quick_5F00_Start_5F00_Guide_5F00_slau709_5B00_1_5D00_.pdf

Please note that with that ADC EVM and the TSW14J56 Rev D the maximum clock rate supported for JMODE0 and JMODE2 will be around 3 GHz or slightly lower. Above that speed there are board related signal quality issues in the JESD204B link that prevent data capture.

Best regards,

Jim B

It looks like there's an additional spur in the noise flow, is this what the output is supposed to look like?

Thank you for your help!  Just one more thing, the part seems to be working now but when I run the sweep described in the user guide (including filtering the RF signal):

I get a lower SNR and DBFs than this seems to indicate:

Here, both are about 8-10 dB lower.  How can I decrease the harmonics?  I'm using a K&L tunable bandpass filter and a Rhode & Schwarz SMA 100 A signal generator.  

Hi Patrick

That preliminary EVM has a pre-production version of the ADC, which does not include final design changes to improve the Fs/2-Fin interleaving spur performance. I think that is the primary factor limiting performance.

To confirm this you can notch out that spur.

1. Click on Test Options>Notch Frequency Bins
2. Then click the check box on the left just below half way down the Filter Parameters popup. This frequency is automatically calculated at Fs/2-Fin based on the ADC Input Target frequency entered on the main HSDC Pro panel.
3. Then click on OK to close the popup. The Fs/2-Fin spur should now disappear, and the resulting SNR and SFDR will be updated.

Please attach a snapshot off the HSDC Pro GUI results once that is done.

Best regards,

Jim B

Oh, that makes sense.  How many bins would you suggest be removed from either side?  I've attached screenshots of 1, 2, and 3.  Their does seem to be a spur at that point.  

Is this in line with what you were expecting?