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ADC12J4000: JESD Issue

Avantx
Prodigy 165 points
Part Number: ADC12J4000

Hi,

I'm using the ADC12J4000 EVM with the provided demo GUI and a FPGA Arria10 board, everything is working well : i can get adc i/q with no problem.

However when I move to my custom hw design, some problems with JESD start to appear:

*My design is a FPGA Arria10 board with ADC12J40000 as ADC and an HMC7044 as clkgenerator.
*I'm using the altera official JESD ip, again no issue when using it with the evalboard (ADC12J4000 EVM).
*On my design, the jesd synchro is never achieved correctly.

What i see:
I'm configuring the ADC12J4000 with exactly the same configuration as the evalboard.
But i observe that the "JESD204B and System Status Register" of the ADC12J4000 (register 0x205) doesn't show a status similar as the Evalboard.
Especially, the bit LINK_UP stays at 0, (bit ALIGNED is 1, PLL_LOCKED is 1).
When reading the datasheet, it only says "When set, indicates that the JESD204B link is in the DATA_ENC
state", it is not really clear about what it means.

What does mean a REG[0x205].LINK_UP at value 0 ?

Is there another register or tests that could help me to find why the jesd is not working?

Could it be an hardware problem? or maybe the ADC12J4000 configuration is not ok ?

Thanks

  • 0
    TI__Guru* 91947 points

    Avantx,

    The TI EVM has all of the serdes P and N signals swapped between the device and the FMC connector to help with routing. If you did this on your board, did you setup the firmware to take this into consideration?

    Another colleague will answer your register questions shortly.

    Regards,

    Jim  

  • 0 in reply to jim s
    TI__Mastermind 44470 points

    Hi Avantx

    Please provide the schematics for your board showing all ADC connections for configuration, power, clocking, etc.

    Please provide the order in which devices on the board are configured. For example is all of the clocking configured, locked and stable before configuring the ADC registers?

    Please measure the voltages applied to the ADC power buses on your board. (VA19, VD12, VA12).

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 165 points
    Hi Jim,

    Thanks for your answers.
    Yes, we have noticed the inversion of P&N on the EVM. We don't have this inversion and took it into account.

    On our board, we power up/configure FPGA first, then HMC7044, then ADF4356, then the ADC12J4000.

    We checked the ADC voltage (VA19, VD12, VA12).

    About the schematics, it there any way to send them to you privately, we can't post this publicly ?

    Thanks
  • 0 in reply to Avantx
    TI__Mastermind 44470 points
    Hi Avantx
    I have sent you a private message to discuss sharing the schematics.
    Regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    TI__Mastermind 44470 points
    Hi Avantx
    I am reviewing the schematics and system block diagram.
    Can you also send me the ADC12J4000 register settings you are writing, in the order used?
    I noticed in your block diagram that you have 2 different possible configurations and serial line rates, but only a single FPGA Device Clock frequency. For each line rate the FPGA Device Clock should be line rate / 40. So for the higher line rate option you should also have a higher FPGA Device Clock.
    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    Prodigy 165 points

    Hi Jim,

    Yes we do have 2 configurations:
    Fs 3932.16MHz or 2457.6MHz
    DeviceClock 122.88 or 153.6

    it was unclear on my blockdiagram
    Okay about the line rate / 40, this is the case.
    Currently we do our tests with the first configuration and one adc.

    Do you have more info about the jesd status register?
    LINK_UP ? Aligned ? Realigned ? flags


    Here is our register configuration (W address value):

    ADC12J4000[0x0001001c] W 0000 bd
    End of register reset

    ADC12J4000[0x0001001c] W 0021 01
    ADC12J4000[0x0001001c] W 0021 00
    End of Digital RST (Emulates a power on)

    ADC12J4000[0x0001001c] W 0021 00
    ADC12J4000[0x0001001c] W 0021 01
    JESD Deactivated.
    ADC12J4000[0x0001001c] W 0201 0e
    ADC12J4000[0x0001001c] W 0000 3c
    ADC12J4000[0x0001001c] W 0002 00
    ADC12J4000[0x0001001c] W 0010 00
    ADC12J4000[0x0001001c] W 0023 7f
    ADC12J4000[0x0001001c] W 0022 ff
    ADC12J4000[0x0001001c] W 0026 3f
    ADC12J4000[0x0001001c] W 0025 ff
    ADC12J4000[0x0001001c] W 0030 82
    ADC12J4000[0x0001001c] W 0030 c2
    ADC12J4000[0x0001001c] W 0032 80
    ADC12J4000[0x0001001c] W 0033 c3
    ADC12J4000[0x0001001c] W 0034 2f
    ADC12J4000[0x0001001c] W 0040 0f
    ADC12J4000[0x0001001c] W 0050 0e
    ADC12J4000[0x0001001c] W 0051 84
    ADC12J4000[0x0001001c] W 0057 11
    ADC12J4000[0x0001001c] W 0058 02
    ADC12J4000[0x0001001c] W 0066 03
    ADC12J4000[0x0001001c] W 0200 30
    ADC12J4000[0x0001001c] W 0202 40
    ADC12J4000[0x0001001c] W 0204 00
    ADC12J4000[0x0001001c] W 0206 19
    ADC12J4000[0x0001001c] W 0207 19
    ADC12J4000[0x0001001c] W 0208 00
    ADC12J4000[0x0001001c] W 020c 01
    ADC12J4000[0x0001001c] W 020d 00
    ADC12J4000[0x0001001c] W 020f 00
    ADC12J4000[0x0001001c] W 020e 00
    Hardware static initialization success !

    JESD Deactivated.
    ADC12J4000[0x0001001c] W 0201 0e
    ADC12J4000[0x0001001c] W 0213 4e
    ADC12J4000[0x0001001c] W 0212 20
    ADC12J4000[0x0001001c] W 0211 00
    ADC12J4000[0x0001001c] W 0210 00
    ADC12J4000[0x0001001c] W 0215 00
    ADC12J4000[0x0001001c] W 0214 00
    ADC12J4000[0x0001001c] W 0216 00
    ADC12J4000[0x0001001c] W 0058 02
    ADC12J4000[0x0001001c] W 0201 5e
    ADC12J4000[0x0001001c] W 0202 c0
    JESD Activated.
    ADC12J4000[0x0001001c] W 0201 5f





    Thanks.

  • 0 in reply to Avantx
    TI__Mastermind 44470 points
    Hi Avantx
    Thanks for the latest information. I am reviewing the information and will respond as soon as possible.
    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    Prodigy 165 points
    Hi Jim,

    We finally manage to make the JESD link working on our custom board.
    The problem was coming from our ADC12J4000 register configuration and from an hardware issue on JESD lanes.

    Thanks for your help.
  • 0 in reply to Avantx
    TI__Mastermind 44470 points

    Hi Avantx

    Thanks for the update.

    I'm glad things are working now.

    Best regards,

    Jim B