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ADC12J4000EVM: Altera FPGA reference design for interfacing ADC using JESD and processing for FFT/FIR at high speed GSPS sample rate

Maddina
Prodigy 10 points
Part Number: ADC12J4000EVM
Other Parts Discussed in Thread: ADC12DJ3200, ADC12J4000

Hi,

We have the requirement of sampling ADC data at 2 GSPS rate in FPGA, and further doing FIR/FFT at 2GSPS sample rate. Please share if there is any reference document/design to capture these ADC data in FPGA at 2GSPS rate. 

  • 0
    TI__Mastermind 43940 points

    Hi Maddina

    There is a reference design on the ADC12DJ3200 device folder that is very close to what you are looking for.

    http://www.ti.com/product/ADC12DJ3200/toolssoftware#softTools

    The "Arria10 + ADC12DJ3200 JMODE0 Design Firmware" provides an Altera Arria 10 example for data streaming into the FPGA fabric. Further processing must be implemented by the customer.

    The ADC12J4000 DDC bypass mode is very similar to the ADC12DJ3200 JMODE0 (single input, DDC bypass mode). The only difference is the sample arrangement within the lanes is slightly different, just a matter of swapping lanes to adapt to the different device. Please refer to Tables 12 and 13 in the ADC12J4000 datasheet, and Table 20 in the ADC12DJ3200 datasheets to see the differences.

    I would recommend contacting Altera to get their recommendations regarding the FIR/FFT implementation.

    I hope this is helpful.

    Best regards,

    Jim B