Hi,
I am using ADC32RF45 at LMFS=82820 in 12 bit bypass mode at 3GHz sampling rate. I try to use the ADC in 12 bit ramp mode however I haven't been able to observe this ramp pattern yet. All I am observing is some mixed data which is definitely not a ramp pattern. However when I use normal ADC data and not connect anything to analog input of the ADC I observe 0s and FFs which is simply noise.
When I use the ADC in 12 bit ramp mode I observe that sync is high almost all the time except very rarely it goes low for 1 core clk cycle at only certain data patterns and goes back high without destroying the code group synchronization . I pass CGS and ILAs phases.
My questions are:
1) what registers should I set specifically for 12 bit ramp pattern. All I am adjusting is JESD digital page register x03 to x01. For the sake of completeness I am also listing other registers in JESD digital page:
Reg Address Reg value
x02 x0F
x03 x01
x037 x01
x032-x035 x00
x01 x80
x07 x0F
x06 x00
x04 x00
2) Why is the sync signal de-asserted very rarely for only certain data patterns. Does it have anything to do with the mixed data that I get at the output instead of a 12 bit ramp data?
If you want I can attach some debug core outputs that show the de-assertion of sync and the mixed data that I get at the output.
I believe I am one step away from getting this ADC to work properly. Any help and/or recommendation is greatly appreciated.
Erdal
