Hello,
I am looking to connect the ADS42JB46EVM to an FPGA demo board running our own FPGA bitstream. I would like to directly control the SPI interface of both the converter and the pll on the EVM, but there is a CPLD in between. I have not been able to find any documentation on how that CPLD is configured. Any documentation which could be provided on the CPLD would be appreciated.
Thanks!
