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ADS1248 Common Mode Question

Other Parts Discussed in Thread: ADS1248, LM7705

I noticed the common mode input range on the analog inputs is rather unusual on the minimum end.  I assume by "Vin" they mean Vref/PGA.

Inserting this into the common mode range formula gives us a common mode minimum of AVSS + 0.1 + (Vref/2).  If I used a unipolar analog supply and the internal Vref 2.048 V, this means the common mode minimum is a rather restrictive 1.124V which will make the part a little unfriendly towards ground referenced single ended measurements.  I did try applying 0.5V and 0V differentially to the analog inputs (i.e. 0.5V single ended), which would be well outside this minimum common mode range, and the digitized result was correct.  Either I am interpreting the minimum common mode formula incorrectly or TI has built a fair amount of margin into this measurement.  Can you verify I have interpreted the minimum common mode limit formula correctly?

  • Hello James,

    Essentially both inputs of the device (AINP) and (AINN) are required to be more than 0.1V from the analog supply rails (AVDD/AVSS).The allowed common-mode range is a function of the differential input voltage, PGA gain and AVDD/AVSS supply range.  The common-mode voltage is defined as:

    VCM = (AINP+AINN)/2   

    The differential signal VIN is given by:

    VINdifferential =  AINP – AINN  

    The Common-mode Voltage Range Limits are given by:

    AVSS + 0.1 + [(PGAGAIN)(|VINdifferential|)/2]  <   VCM   <   AVDD - 0.1 - [(PGAGAIN)(|VINdifferential|)/2]  

    The requirement is that both the AINN and AINP should be more than 0.1V from the rail supplies AVSS and AVDD. Depending on the maximum PGA Gain that you plan to use and maximum differential signal applied; the allowed common-mode range may be calculated. 

    Below is a link to a Design Note for the ADS1248 and ADS1148 families that discusses the common-mode requirements and provide some examples. I usually place the equations on a spreadsheet  like excel to easily calculate if the circuit is in the allowed voltage range

    Regards,

    Luis 

    http://e2e.ti.com/support/data_converters/precision_data_converters/w/design_notes/input-voltage-range-requirements-for-the-ads1248-and-ads1148-families.aspx

  • Like James I am struggling with the formula for the common-mode range for the ADS1248. In our system we are using AVDD = 5 V, AVSS = -0.232 V, along with an external 3.0 V voltage reference and want to measure ground reference signals in the range of 0 to 2.5 V without doing any level shifting. In hardware this works fine with PGA gain = 1, even though the common-mode voltage range limit formula (equation 4 on pg. 26 of ADS1248 data sheet) says it won't or shouldn't work. I often work with discrete differential programmable amplifiers as illustrated in Figure 53 of the datasheet to represent the ADS1248 PGA, and believe that while equation 4 is valid for PGA gains > 1, it is wrong for PGA gain = 1, at least for the circuit in Figure 53. For a PGA gain = 1, the common resistor between the differential op-amps would be open and so the AI amp output would essentially be AINN and the A2 amplifier output would essentially be AINN, i.e. just voltage followers. Then as long as AINN and AINP are within the +/- 0.1 V supply headroom requirements the PGA illustrated in Figure 53 things should work fine, even though equation 4 says other wise because of the Vin*Gain/2 terms. I believe that for PGA gains > 1, then these Vin*Gain/2 terms apply and equation 4 gives correct results, but not for a PGA gain = 1. Of course I could be all wrong and would be pleased to learn of my error in thinking. Yet we hope that we can use the ADS1248 to measure ground referenced input voltages from 0 V up to 2.5 V in the system described above without having to resort to split supplies or level shifting to some bias voltage. If we can't do that they we may have to switch to another ADC. As previously mentioned, the measurements work fine in hardware, and I am seeking to know if the approach described is a solid approach or not. Again, I cannot understand why equation 4 for the common-mode range of the ADS1248 would apply for a PGA gain = 1, as I don't think it applies for the amplifier configuration illustrated in Figure 53 for a PGA gain = 1.

    Thank You.
  • Dear Jody,

    welcome to our forum and thank you very much for your question.

    Short answer is: Your setup is perfectly fine to measure ground referenced signals with PGA=1 and it is also meeting the common-mode voltage requirement equation.

    I assume you are using our LM7705 to generate the negative AVSS supply?
    We are currently working on a reference design (TI Design) using ADS1248 + LM7705 that we will release soon showing exactly what you are implementing.

    As you correctly mentioned when using a gain of 1, the outputs of each amplifier - and thus also the inputs - need to stay 100mV away from the rails.
    The only point that I guess does confuse you is that the common-mode voltage needs to meet the equation. The common-mode voltage of a ground referenced signal is in the end VAINP/2=VIN/2. So in case you want to measure a 2.5V signal the common-mode voltage would be 1.25V.
    The common-mode voltage equation says: VCM >= AVSS + 100mV + VIN x Gain / 2 = -0.232V + 100mV + 2.5V/2 = 1.118V.
    As you can see the common-mode voltage of 1.25V is meeting this requirement. Means you are fine with your setup.
    You only need to check that you meet the equation at the maximum input signal that can occur in your application.

    I prepared attached presentation which hopefully also helps to clarify things:

    PGA Common-Mode Voltage Limitations.pptx

    Regards,

  • Thank you for the informative response. Yes we are using the LM7705 to get a slightly negative supply, which then works great so that the ADS1248 can measure 0 V well. My confusion stemmed from forgetting that the equation 4 mentioned is for common-mode voltage, and not the minimum or maximum voltages which can be applied to PGA inputs. As you pointed out for a ground referenced signal the common-mode voltage is simply Vin/2, which for a gain of 1 always exceeds AVSS + 0.1 V + Vin/2 in our system since AVSS = -0.232 V. Thanks for straightening me out, and glad to hear that the LM7705 approach for AVSS is considered a good approach.

  • Dear Joachim,

    OK, I understand that it is important to meet this in order not to increase the integral nonlinearity and the offset voltage. And your explanation is really good.
    But I made a design without following this rules and the measured values seem to be quite good.
    (AVDD: 5V, AVSS 0V, PGA = 1, Input: 0-2V).
    The solution with the LM7705 seems to be the best way.
    But can you specify the additional errors if we still violate this rules ?
    Or do you know designs which violate this rules too and work acceptable ?

    Regards

    Klaus Schmidt
  • Klaus,


    It's very difficult to quantify the error when the input common-mode is violated. To the first order, this is like having the input stuck about AVSS, so it is similar to a large offset.

    However, the input is similar to the front end of an instrumentation amplifier and the error is going to depend on a great many things. The error may depend on the temperature because we've put the input of the amplifier into a non-linear range of operation. Since one of the amplifiers is out of range, it may have a different response than the other. There may be unusual behaviors because the input is chopped to reduce the original offset.

    In short, we've never characterized this as an input. It is outside the range of normal operation and may be unpredictable. I'm sorry I can't give any more guidance on this operation.


    Joseph Wu
  • Hello Joseph,

    I thougth it would be a chance. OK, we will add the LM7705 to the design. Then we have all done to meet the specifications.

    Thanks

    Klaus Schmidt
  • Wow -- that clears it all up nicely! TI should have a link to your powerpoint in every adc-with-pga datasheet.

    thx, gil