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ADS79xx SPI timing

James Thorne
Prodigy 20 points

From what I can tell, the ADS79250 family uses SPI mode 0, since it latches input data on the first clock edge, which is a rising edge.  The data sheet says it supports a 20MHz SCLK for 3V VBD, but the td2 max delay is 27, which means the SDO may not be valid on the rising 20MHz SCLK edge, requiring you to sample it on the following falling edge.  Since SDO changes a set time after the SCLK falling edge, you could sample SDO on the falling edge, but that would mean the ADS is not operating in the same SPI mode as the master device.  So can I just use SPI mode 0 for both as long as I have a 14MHz clock or slower, and set the CS related delays?

Thanks,


James

  • 0
    TI__Expert 5705 points

    Hi James,

    You are correct assuming SCLK has a 50% duty cycle. However, as there are no restrictions on duty cycle other than the requirement that SCLK's high/low time be >= 20ns, it would be acceptable to make the low time of SCLK = td2 max (35ns worst case @ VBD = 1.8V). In this case, SCLK would have a period of 55ns or a frequency of ~18MHz. I think this may even get you 1MSPS throughput; (tsu1 + 15*tsclk + 20ns + td3 + tq) < 1uS

    Thanks,
    Harsha

  • 0
    Prodigy 100 points

    I would just like to point out that all SPI buses, regardless of mode, transmit on one edge and receive on the other.  SPI mode 0 uses the rising edge for SDI and the falling edge for SDO.   Regarding the timing:  I can see that DO happens 27 ns after chip select at which time you are supposed to clock DO in using the negative edge.  The setup time between CS going low and the first clock edge is 6 ns so you need to subtract that from the 27 which gives 21 ns.  So if you are running with a skewed duty cycle of 20 ns then it will miss by 1 ns under worst case conditions.  You can avoid this by guaranteeing you duty cycle doesn't produce that big of a skew.  The hold time for the data output DO after the clock edge goes low is 5 ns which is a little challenging but not bad.  Given all this, I think the timing should be easy to meet.