Can I tie HVSS to AGND, when I use ADS8634 to convert input range of 0V to 10V?

Hey

I am suing ADS8634SRGER in the design with SPI interface. Without connecting any Analog input to this ADC I am getting 800 value on my SDO line. Even if i give a voltage at the input i am getting 800. 

Please suggest if anyone had faced this issue.

This information is too less to understand what is happening.

If you apply some voltage to input, you should surely get someting. That means there is something wrong with your setup.

Can you give more information about the condition, moeds etc?

Is the "800" in hex or decimal? Is the value is solid "800" (no distribution around 800) or it is average value?

If "800" is in hex, then it means your are reading midcode. Now in any bipolar mode if AINp and AINgnd are "zero" then output should be around mid-code. But it should have some distribution around "800".

Above image is the schematics and DSO output & -12 and +12V is HVSS and HVDD.

We are using SPI mode 3 and you can see the value 800 in the DSO output.We are probing SCLK and SDO pin of the ADC. Is there any register so that we can read the digital value.

We have a DAC in our system and output of this DAC is connected to the input of ADC. 

In the above case we are using 0-10V reference (internal).

At this moment I can suggest some basic checks like,

1) Check/measure manually all Supply pin/ Ref Pin/ Analog input Pin voltage to make sure that everything is proper. Device powers up with external reference mode. So you need to enable internal reference through register programming to use it.

2) Please try to program some internal register (like addr-10h, 11h, 12h, 13h - they are range programming register) and read them back and check if you are reading correct values. This is to ensure that pattern are corrects

3) Try to run different scan mode like manual mode/ auto mode and check if it is responding to anything. If any channel is selected then at sampling instance there will be small kick back on that channel which should be visible in oscilloscope and this can verify the channel selection is correct or not.

I have tested all the supply Pins. Everything is fine. We have enabled internal reference voltage too.

We programmed internal register and read back the values through commands. Its writing properly.

We are running manual mode. 

I did not understand what is that Kick back. 

If I measure the SDO line in the first set of clocks will I get the expected output.

You can try to switch different channel and you can try to see if channel selection is happening correctly or not.

What I meant by kickback, if channel is selected then at sample start and sample end time instance, you should see a kickback on the analog input. It should be visible in oscilloscope. Only selected channel should show this and other unselected channel should not show this. By observing this you can makeout whether channel selection is happening correctly.

If everything is correct then only thing comes to my mind is that you can try with another device. (cause during all these debug if the device is damaged somehow.)

On SDO line first 4 bits are channel address and then data bit comes out. Looking at channel address also you can make out whether channel selection is correct or not.

Hi, Thanks for your reply

Now our ADC is working fine and we are another issue coming up.

We have 0.3V difference the input analog value and what we are getting as digital output.

We are using SMPS for +/-12V i.e HVDD and HVSS. But I am able to supply get +12V and -11V to the ADC due to some drop in the negative side value.

Is this acceptable ?

Or I need to make both the value as same like +12 and -12V.

Am I getting 0.3V between my input and output because of this ?

HVDD, HVSS as +12V and -11V will work.

0.3V offset between analog input and adc output should not be from the supply difference.

Please check your INP measurement is with respect to AINGND.

The ADC is converting (AINP-AINGND). So the output value will be with respect to AINGND.

If your AINP path has any external resistor, it may be good idea to have same resistor in AINGND path also.

Above is the schematics diagram of the ADC interface.

We have used a OPAMP. External resistor we have used here is 20E.

Does this causing a problem. So connecting 20E in series with analog ground should solve the problem according to you.

In place of the inductor on the AINGND path I would prefer to have a 20 ohm resistor grounded in parallel with 1200pF cap. This should match the impedance of AINP and AINGND path. That should surely reduce any systamatic offset.

But I don't know if there are other issues present in the board. But to start with you can check this suggestion. Atleaset to start with try with only 20E resistor and see if the offset is reducing.

One doubt?

Do you see the 0.3v is pure offset of the channel that means it is present through out the input scale?

Thanks for your input, I will test it by changing to 20E instead of inductor.

No the value 0.3 is not a constant offset. It varies.

What it (0.3v offset) varies with?

Does it vary from channel to channel if then how much?

Does it vary with analog input scale if then how much?

Please share whatever observation you have regarding this.

Thanks for your quick response sir.

1.what it (0.3v offset) varies with?

- > It varies between the conversions.

2. Does it vary from channel to channel if then how much?

- > Irrespective of channels. It varies between conversions.

3. Does it vary with analog input scale if then how much ? 

-> No it doesnt.

What i observed is first conversion will give us a accurate result. ie. when I 7.5V i get 7.479V.

But when I keep repeating the conversion the value is getting decreased.

The sequence of conversion values are like follows...IRRESPECTIVE OF CHANNEL SELECTED.

Input : 7.5V

Then it goes like this

7.440

7.426

7.360

7.338

7.323

7.316

7.306

7.296

7.294

7.261

7.283

7.286

7.284.

I have also tested by changing the inductor to 20E and did not see any difference.

Please find my observation in the following message.

I have also tested by changing the inductor to 20E and did not see any difference.

Please find my observation in the above message.

Bhanuprakash,

Dipankar and I spoke about this behaviour you are seeing. We need to figure out if this gradual degradation or droop in the converted voltage is happening at the Analog Input or inside the ADC.

Two quick checks to help narrow down on the issue:

 1. We assume you have tied all the driver op-amp inputs to a single 7.5V. If you are toggle between two channels and observe the voltage at the capacitor on the analog input pin of one of the channels using a scope, is this gradual droop observed on the scope as well.

 2. Does the rate of the droop change when the sampling rate of the ADC is changed?

Thanks.

Regards,

Sandeep