• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 46 subscribers
  • Views 425 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Two questions about ADS7850

LI XIANG
Intellectual 445 points
Other Parts Discussed in Thread: ADS7850, ADS8350

 I have two questions when I try to use this IC(ADS7850). 

 

As you know, generally speaking an ADC will have two stages, one is conversation stage to convert analog data to digital data, and another stage named acquisition stage which is to shift the digital data out through serial or parallel interface. Both those two stages need an SCLK. So my first question is can I use two different frequencies SCLK in the mentioned two stages respectively, such as I will involve an 20 MHZ for conversation stage and 15MHZ for acquisition stage. Will this behavior bring some potential issue to the ADC?

 

The second question is: what is the setup time from SCLK falling edge to the output data valid? I can only find a items that setup time from SCLK falling edge to previous data valid, but this will not make sense. I need to know the time from SCLK falling to current data valid.

  • 0
    TI__Guru 52446 points

    Hi Li,

    In the ADS7850, CS is used to trigger the conversions, where the ADS8350 enters conversion mode right after CS toggles low and remains in conversion mode for a max period of 590ns.  The device enters acquisition mode immediately after the conversion mode and remains in acquisition mode until the next falling edge of CS (until next conversion).  The device is by default in acquisition mode, until the user triggers the next conversion.

    During the acquisition phase, the analog input signal is allowed to charge the ADC’s sample-and-hold capacitor to a level proportional to the analog input.  The input circuitry must be able to settle and charge the sample/hold capacitor to ½ LSB during the acquisition period.  The application section of page 27 discusses the requirements for an optimal amplifier or driving circuitry.

    As you mentioned, during the conversion phase, the sample-and-hold capacitor is disconnected from the analog input and converted to a digital code with the internal CDAC.

    For example, using the device with the max supported SCLK frequency 24MHz,and max throughput 750kSPS, the acquisition time will be approximately:

    tACQ = tTHOUGHPUT- tCONV = 1.33us-590ns = ~743ns

    Normally, a constant SCLK freq is used during the acquisition and conversion period during the serial frame, where SDO-x will always shift the conversion data after the 15th SCLK falling edge. 

    What is the reason the application requires two different SCLK frequencies, during the conversion and acquisition phase?  Notice, the user can control the length of the acquisition period and the throughput rate by controlling CS.  If the maximum 750kSPS throughput is required, the user will have to set SCLK to the max 24 MHz frequency.  In this device, the conversion period is not controlled by SCLK. 

    On question (2), the spec for set up time from SCLK falling edge to next data valid is a maximum of 20ns.  This timing spec needs to be updated into the datasheet in an upcoming datasheet revision.  Many thanks for the feedback.

    Best Regards,

    Luis

  • 0 in reply to Luis Chioye
    Intellectual 445 points

    Dear Luis,

    Thanks a lot for your reply, and it helps me a lot.

    For the first question, the reason that I want to use two different frequency sclk is: in my system, the system clk is 125MHz, and sclk is required to be 50% duty cycle. What is more, I hope to hit 512KSPS (1.95us) sample rate.During conversation stage, I just want to hit the 590 ns and 14 sclk cycles requirement and finish it as quick as possible. However in acquisition stage, I need to use 15.6MHz (125/8) to sample the data at the best sample point (Here I take cable, buffer, logic propagation skew into consideration).

    Actually the most important thing is the second question, your reply really helps me a lot. Now I can use this parameter to calculate one more time to find the best sample point and decide my sclk frequency.

    However, I still have some questions need your help.

    • Does the propagation delay skew affect by environment?  Any drift on time and temperature?
    • Is it purely part-to-part variation? Please provide the distribution.
    • 17ns (20 - 3) skew is un-reasonable for a 24MHz device.  Any plan to improve?

    BTW, I also find another problem in the datasheet page 9, the sclk lable 1, 2, 3... to 28, and then there is no 29 but two 30.

    Thanks,

    Best Regards,

    Jason Li