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ADS1248 wreg rreg not reading back register

Chris Forte
Intellectual 310 points

the rreg command always returns '0'

Here is the timing of the wreg writing 0xaa to MUX0 register:

Here is the timing of rreg for the same register MUX0:

  • 0
    TI__Guru* 92715 points

    Chris,

    In general, your communications look correct. Data looks like it's clocked in on the falling edge of SCLK and the command seems right. There are two things that I'd point out however. First, what is the time scale? Note that the SCLK period should be no shorter than 488ns. Any faster than that, and you may not correctly clock in anything to the device. The second note is that we generally have DIN, dwell low. I don't think this is a likely problem, but I thought I point that out.

    One thing to try is to clock out a different register that you know will have something in it. I'd clock out the FSC register that holds the full-scale calibration coefficient. You know that there will be a non-zero, not all-1's result there.

    Let me know if any of these comments help you out. Feel free to post back to this thread.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Intellectual 310 points

    Joseph,

    The time scale is 160ns. My SCLK = 2mhz (500ns). 

    Din according to datasheet pg. 26 should output NOP which is all hi.

    Some additional info:

    My external CLK is 1Mhz. Is this a problem?

  • 0 in reply to Chris Forte
    TI__Guru* 92715 points

    Chris,

    That's the problem. The SCLK is too fast for the device to be run with an external 1MHz CLK. The Timing Characteristics for Figure 1 are based on a 4.096MHz clock.


    Internal to the device, the SCLK gets latched in based on a divided CLK signal. If the SCLK is faster than the CLK, you'll miss a lot of the SCLK pulses.

    With an external CLK of 1MHz, you'll need to run the SCLK slower, say near 500kHz. A different test that you can try is to disconnect the external clock and tie the CLK pin to ground (this will return the device operation to the internal oscillator, running near 4MHz). Make sure that this is done before starting up the part. In that case, you can run SCLK at the same 2MHz.

    Joseph Wu

  • 0 in reply to Joseph Wu
    Intellectual 310 points

    Joseph,

    I decided to use the internal CLK and this solved the problem.

    Should TI rev the datasheet to indicate that CLK must be 2x SCLK min?

  • 0 in reply to Chris Forte
    TI__Guru* 92715 points

    Chris,

    Thanks for getting back - I'm glad you were able to find a solution.

    I'll discuss changing the datasheet with people here. In the end, the Timing Diagram does mention that the specifications are for a 4.096MHz CLK. It may need to be pointed out that the characteristics scale with clock frequency.

    Let me know if you have any other questions.

    Joseph Wu

  • 0 in reply to Joseph Wu
    Intellectual 310 points

    Joseph,

    Once again I am experiencing a constant '1' when trying to read any register. Nothing has changed in my design. I am using the internal CLK and a SPI sclk of 1mhz. 

    Same timing diagrams as before.

  • 0 in reply to Chris Forte
    TI__Guru* 92715 points

    Chris,

    I would start by regenerating the same timing diagrams just to make sure. I'd like to know if the part responds to anything at first.

    Check that START is high and /CS is low. Then track the SCLK, DIN, and DOUT lines. If you have another line check to make sure that /DRDY is giving regular pulses. This will indicate that the part is alive and kicking out data regularly.

    Joseph Wu

  • 0 in reply to Joseph Wu
    Intellectual 310 points

    Joseph,

    Here I try to read register OFC1 (x05). SCLK is 1mhz

  • 0 in reply to Chris Forte
    TI__Guru* 92715 points

    Chris,


    Could you try reading back a different register? The OFC can often start with FF because it's a two's compliment notation and that would indicate a slightly negative value. In that case having OFC1=FF would not be unusual. (Granted you're reading the middle byte but the point is the same).

    I would pick something in the first four registers to write to and read back from. Set the data rate to 160 SPS in the SYS0 register and then read it back.

    Again, your plots generally look correct. Let me know how the SYS0 write and read work.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Intellectual 310 points

    OK, working fine.