This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1293 Operating Voltages - VDD vs VDDIO (5.0 VDC vs 3.03 VDC)

Other Parts Discussed in Thread: ADS1293

In my application of the ADS1293, I am driving VDD and VDDIO with the same 3.03 VDC source voltage.  What I noticed is that I need to drive at least a 200mV differential on the inputs to a channel in order to see my ECG waveform (using a Dale ECG simulator).

Typically, in a Holter application, the electrodes deliver a typical 3 to 5 mV differential.  When this is applied to the inputs, I get a flat line for output.

Using the TI EVM, this same input gives us a nice output waveform as expected.

Following up on that, we decided to boost our VDD to 5.0 VDC matching that of the EVM and voila, the 3 mV differential input suddenly showed up at the expected output levels on our own design.  We need to run at 3.03 VDC from a single source and need to conserve power.

So, it seems the internal VREF has an (undocumented?) relationship to VDD. 

Why can't I drive both VDD and VDDIO at the same level and at 3.03 VDC to get my expected behavior?

I notice that I can disable the internal VREF and drive my own VREF to the CVREF pin. 

What should I be doing to operate this chip properly at 3.03 VDC on VDD and VDDIO and be able to properly handle electrode inputs all the way down to 500 uV differential as the specs require us to?

Thanks!

Almost forgot... we are driving a 5-wire input and providing a 3-channel recording (LA-RA, LL-RA, V1-Wilson).

  • For the sake of others I will answer my own question (after spending a couple days doing some homework).

    It seems the chip will work well at 3.03 VDC on both VDD and VDDIO.

    The cause of the quirky behavior was that the analog ground (AG) was 1.5 VDC above DGND.  So the analog section of the chip was only operating at about 1.5 VDC which is below chip spec.  When we bumped the VDD to 5.0 VDC, that brought the delta voltage on the analog section up to 3.5 VDC (5.0 - 1.5).  This is why things appeared to start working.

    Once the chip was powered properly and AG was tied to DGND (via proper decoupling) the VREF went to 2.40 VDC as it should have.

    On to the next set of issues.