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ADS1278-HT: Verbose CLK Input Pin Requirements?

Andy Gauvin
Prodigy 10 points
Other Parts Discussed in Thread: ADS1278-HT, ADS1278

Hello,

What are the verbose CLK Input Pin requirements for this device, apart from the frequency capabilities and requirements that have been well-defined in the datasheet? (ADS1278-HT SBAS447E –MARCH 2009–REVISED APRIL 2013)


Specifically,

  1. What voltage levels is this pin expecting to function correctly and avoid device destruction? 0-DVDD or 0-IOVDD...?
  2. Does this pin expect a standard CMOS clock input?
  3. What duty cycles are recommended to maintain conversion accuracy of the chip? Would a 55/45 CMOS signal be compatible, or should this signal be manipulated to ensure 50/50 duty cycles?
  4. What relevant pin/circuitry parasitic should designers be aware of, apart from the recommended 50Ω series source termination already identified in the datasheet? (eg, input impedance/bias currents, input capacitance, internal pullup/downs).

Thank your for your assistance,

-Andy Gauvin

  • 0
    TI__Guru 57346 points

    Hello Andy,

    Thank you for your question and welcome to our forum! I'm sorry that we did not answer you sooner. I will offer my inputs below and I hope they can still be helpful:

    1. The CLK input is expecting 0V to IOVDD (typically 3.3V). DVDD only powers the digital core of the ADS1278. Table 7 in the datasheet may mislead you to think that CLK is dependent on the DVDD level, but in fact we are showing that the digital core requires a little more power at the fastest CLK rates, so a higher DVDD is needed here.
    2. Yes, the CLK pin is a standard CMOS input. What was your concern here?
    3. The duty cycle for the CLK input is not given as a percentage in this part; rather, we specify the duty cycle as a minimum pulse width (tCPW) = 15ns. For a 27MHz clock, this would mean at least a 60/40 duty cycle; however, for a 5MHz clock, you can get away with a 90/10 duty cycle. In the ADS1278, the modulator clock is produced using clock dividers, which clean up the input clock duty cycle, to an extent. 
    4. The 50 ohm series termination should be sufficient to help with unwanted ringing. In addition, ensure that you use a low-jitter clock source.

    Best Regards,