• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 46 subscribers
  • Views 356 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Question on ADS1274 SPI Interface

Hak-Jin Jeong
Intellectual 350 points
Other Parts Discussed in Thread: ADS1274

Hello

I have plan to use ADS1274.

According to figure 88 in the datasheet,

DOUT1 is connected through D-flip-flop to DSP.

I also found this D-flip-flop in the ADS1278EVM Schematics too.

If I use SPI instead of Frame-Sync, Can I remove D-fliplflop from my design?

Is this D-flip-flop only for Frame-Sync mode?

With ADS1278EVM, User can select SPI or Frame-Sync mode, but DOUT1 has always D-flip-flop.

So, I am not sure whether I should D-flip-flop also.

and, Is there any detail information about why D-flip-flop should be used even in the Frame-sync mode.

( I couldn't understand why it is necessary)

Thank you for your help in advance.

Best Regards

Hak-Jin Jeong 

  • 0
    TI__Guru 60866 points
    Hello Hak-Jin,

    Thank you for your post!

    Both SPI and Frame-Sync mode allow you to output data in Discrete Data Output Mode. This uses one pin (DOUT1) to output all of the channel data. To do this requires a faster SCLK, and you may find that a faster SCLK violates some of the required timing specs. To avoid losing data, the D flip-flop is used to hold and re-clock the previous bit to the microprocessor.

    You can refer to this post for more details: e2e.ti.com/.../1363539

    Let me know if this helps. If you are still unsure, please provide your master CLK, data rate, and SCLK settings for your application. :)

    Best Regards,
  • 0 in reply to Ryan Andrews
    Intellectual 350 points

    Hello,

    I have one more question.

    If D-flip-flop is used, DOUT1 will be delayed about half period of SCLK.

    How does SPI Master process this data delay?

    Best Regards

    Hak-Jin Jeong