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ADS1256 does not initialize reliably

VG
Intellectual 620 points
Other Parts Discussed in Thread: ADS1256, ADS1255

CPU: TM4C123G Launchpad

SCLK: 1 Mhz 

ADS1256 Oscillator: 7.68 MHz (Asychronous to CPU) 

If I try to initialize the ADC with just the data rate command (ie 0x53, 0x00, 0x82) it seems to work ok.  I see DRDY pulse every 10 ms as requested.

However, if I try to write multiple parameters (ie 0x50, 0x03, 0x00, 0x01, 0x82) DRDY does not always pulse every 10 ms.  

I have verified t6 and t11 timing per the datasheet and everything looks ok.

What am I doing wrong here?  Please see event table and screenshot below.

 Time  MOSI
-1.20E-06  FE 
1.99E-01  50 03 00 01 00 82 
2.00E-01  54 00 06 

  • 0
    TI__Mastermind 44610 points

    Hi Vincent,

    Do you send the SDATAC command before writing to the registers?
    The ADS1255 defaults into RDATAC mode so an SDATAC command is needed to put the device into a state where you can write to the registers. I have noticed that sometimes WREG commands can still take effect in RDATAC mode, but not reliably.

    Otherwise, your timing looks correct.

    Best Regards,
    Chris

  • 0 in reply to Christopher Hall
    Intellectual 620 points

    Chris,

    Thanks for your quick response.

    I tried sending 0x0F (SDATAC) as you suggested, but I am still not getting the correct response.

    Any ideas?

    Thanks,

    Vince

  • 0 in reply to VG
    TI__Mastermind 44610 points
    Hi Vince,

    It looks like you're sending 50h, 03h, 00h, and then writing to only 3 registers...in that case the command sequence should be 50h, "02h", 00h.

    When /CS goes high the WREG command may not be taking effect since it is being terminated early. Try that small fix and see if things work better...

    Best Regards,
    Chris
  • 0 in reply to Christopher Hall
    Intellectual 620 points

    Thanks again for your quick responses.

    I tried the change you suggested and it is still not working.  I noticed some behavior on the drdy line about 26 ms later.  In the end it is still not working.

  • 0 in reply to VG
    TI__Mastermind 44610 points

    Hi Vince,

    Wait a minute... you have separate "SCLK" and a "CLK" signals shown on the scope screenshots that seem to follow each other. Is the "CLK" signal not a continuous 7.68 MHz clock?

    Best Regards,
    Chris

  • 0 in reply to Christopher Hall
    TI__Mastermind 44610 points
    ...Maybe the "CLK" signal is your "SCLK", and I'm just seeing different signal labels for the oscilloscope decoding.

    However, I would check the 7.68 MHz "CLKIN" signal to the ADS1256 to make sure that this clock is stable. As long as the device is powered-up and a "CLKIN" signal is present, /DRDY should not stop as you've shown in the last screenshot.

    BR,
    Chris
  • 0 in reply to VG
    Intellectual 620 points
    SCLK is the digital version of CLK. They are both measuring the SPI clock.

    For clarity:
    SS is the same as CS
    The two MOSI signals are the same.

    Sorry if I caused any confusion.

    I will measure CLKIN as you suggest.
  • 0 in reply to VG
    Intellectual 620 points

    I used the channel for MOSI to measure CLKIN.  I don't see anything unusual.

    Something I would like to reiterate from my original post is that CLKIN is asynchronous from SCLK.  Could this cause an issue?

     

  • 0 in reply to VG
    TI__Mastermind 44610 points
    Hi Vince,

    CLKIN looks to be about the nominal 7.68 MHz... No problem there!

    Are you still seeing the /DRDY signal go "quiet" for moments at a time?
    If so, the /RESET and /PWDN pins aren't doing anything unexpected, are they?

    Best Regards,
    Chris
  • 0 in reply to Christopher Hall
    Intellectual 620 points
    My concern with my last post is that I sent a command to set the data rate to 100SPS and the ads1256 did not respond!!!

    I have looked a the /RESET signal in the past and there were no issues. I will look at /PWDN. Any other ideas as to what is going on?
  • 0 in reply to VG
    Intellectual 620 points
    Ok I just checked my schematic and /PWDN is tied to 3.3V.

    Any ideas?
  • 0 in reply to VG
    TI__Mastermind 44610 points
    The only thing that comes to mind is to add a small delay between /CS going low and you're first SPI command, just to ensure that the first SPI command issued after /CS low is being decoded properly by the ADS1256. Everywhere else in the SPI communication seems to have a sufficient delay time.

    Best Regards,
    Chris
  • 0 in reply to Christopher Hall
    Intellectual 620 points

    Sometimes the ADC will respond to the 100SPS DRATE command and other times it will not.   Would be possible for you to set up a system with the same interfaces I have and evaluate?  I'm kinda stumped.  

    Next I am going to try to use a CLKIN that is sychronous with SCLK.  The drawback to this is that the Tiva device I am using will generate a 8 MHz clock rather than 7.68 MHz.

  • 0 in reply to VG
    TI__Mastermind 44610 points
    Hi Vince,

    Can you send me your code so I can try to replicate it exactly? You can email it to pa_deltasigma_apps@ti.com. I have a different TIVA LaunchPAD I can try it on.

    The delay I was referring to was the delay between /CS falling edge and SCLK rising edge (BEFORE you sending commands - you highlighted the delay AFTER sending commands on the oscilloscope screenshots).

    There shouldn't be any issue using an asynchronous SCLK and CLK, as long as the setup and hold times meet the ADS1256 timing requirements.

    Best Regards,
    Chris
  • 0 in reply to Christopher Hall
    Intellectual 620 points
    Chris,

    I sent you the code. Please let me know if you got it.

    Thanks,

    -Vince
  • 0 in reply to VG
    TI__Mastermind 44610 points

    Hi Vince,

    I got your code via email, it's odd that it didn't appear in E2E though...I’ve looked through the code and I don’t see any issues. I’ll try to see if I can connect some hardware to test it out…

    Meanwhile, would you be able to try adding a 50 Ohm series resistor to your SCLK signal?

    I’m concerned that the ADS1256 may be seeing an extra SCLK occasionally. This may not be show up on the oscilloscope because the oscilloscope is bandwidth limited. It could be that you code is fine, but there is a signal integrity issue that is interfering with the SPI communication. A small series resistor on the SCLK signal will provide a bit of filtering to keep the SCLK signal clean.

     

    Best Regards,
    Chris

  • 0 in reply to Christopher Hall
    Intellectual 620 points

    I added the resistor.  The issue is still present.

  • 0 in reply to VG
    Intellectual 620 points

    Chris,

    It looks like you were right about it being a signal integrity issue. I added 270pf of capacitance to SCLK and everything seems to be working reliably now.

    Thank you for patiently reviewing my signals and my code and advising me along the way. It was very helpful.

    -Vince

  • 0 in reply to VG
    TI__Mastermind 44610 points
    Hi Vince,

    That is a great find on your part!

    It sounds like you've at least got a good solution for now; however, I hope your final solution fixes the signal integrity issue and doesn't need to rely on that capacitor. If you are planning to do a re-spin of your PCB, I'd be glad to review the ADC layout and provide my feedback.

    Glad I could help,
    Chris
  • 0 in reply to Christopher Hall
    Intellectual 620 points

    Chris,

    I agree that we shouldn't need the capacitor.

    Thanks for the offer to review our layout.  When the time comes for a board spin I may take you up on it.  For now, would it be possible for you to send us a reference layout for this device?

    Thanks,

    -Vince

  • 0 in reply to VG
    TI__Mastermind 44610 points

    Hi Vince,


    Sure, not a problem!

    The ADS1256EVM is the probably the best reference layout I can point you to at the moment. You can find ADS1256 reference material, including the ADS1256EVM Gerber files, here:

    Best Regards,
    Chris