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Read error RDATAC ADS131E04

Other Parts Discussed in Thread: MSP430F249, ADS131E04

I'm trying to implement a data acquisition system with MSP430F249 and ADS131E04.

ADS131E04 configuration:

- Internal reference
- Internal Clock
- 64 ksps
- 16-bit
- 4 Channels

Currently I have to run the RDATA way to 100%.

But when I use RDATAC so, I can not get the correct data.

My sequence can of instructions is as follows:

1) Reset ADS131E04 (by command)
2) Send SDATAC
3) Set ADS131E04
4) START (by command)
5) Send RDATAC
6) Check DRDY
7) Receive data
8) STOP (by command)

Do you have any solution to my problem?

Greetings,

Carlos Martins

  • Hello Carlos,

    What do you mean when you say you cannot get the correct data? Can you provide details of your setup i.e. schematics, voltage inputs, etc.?

    Regards,
    Brian
  • Hello,

    For testing purposes I am trying to measure 2.5V with only one ADS131E04. With RDATA so I can get data perfectly, but with the RDATAC so I can not get correct data.
    I've attached my electrical schematic, and images of SPI communication.
    I want to set the ADS131E04 to 4 channels, internal reference 4V, internal clock and 64ksps.

    SPI configuration:
    CPOL = 0
    CPHA = 1
    Baud rate: 8 MHz

    ADS131E04 configuration:
    Id = 11010000
    Config1 = 10010000
    Config2 = 11100000
    CONFIG3 = 11100000
    FAULT = 00000000
    CH1SET = 10000000
    CH2SET = 10000000
    CH3SET = 10000000
    CH4SET = 10000000
    FAULT_STATP = 00001111
    FAULT_STATN = 00001111
    GPIO = 00001111

    My command sequence:
    1) Reset ADS131E04 (by command)
    2) Send SDATAC
    3) Configuration ADS131E04
    4) START (by command)
    5) EnviarRDATAC
    6) Check DRDY
    7) Receive date
    8) STOP (by command)

    In the measurement results get random values for STAT, CH1, CH2, CH3 and CH4.

    Greetings

    Carlos Martins

  • Hey Carlos,

    Would you mind zooming in on one of the sequences where you collect the data?

    Brian
  • Hello Brian,

    My Oscilloscope has some limitations, so I can not get a complete data transfer with a good resolution.

    But I can show you a part of that transfer through the figure attached.

    Greetings,
    Carlos Martins

  • Hey Carlos,

    I understand now what the problem is. You are not shifting out data quickly enough and it is being overwritten by subsequent samples. You can really see this in your second scope image above. The period between DRDY edges will be roughly 16 us when in the data rate you have configured the device to. It takes you 44 us to shift out data. This means that your data will be corrupted when the next DRDY pulse occurs.

    The reason this works fine in SDATAC mode with the RDATA command is that the device does not automatically load new data into the output shift register in that mode. However when you use that mode, it's likely that you are missing samples.

    To fix this you will have to make your SPI routine much more clean; you will need to trigger quicker on DRDY, reduce the time between SCLK bursts, and perhaps make SCLK faster. Alternatively you could use a slower data rate.

    Regards,
    Brian Pisani
  • Hello Brian,

    First of all thank you for your help, you were right about my SPI routine. I corrected my SPI routine and now I can work with RDATAC mode 32ksps. However, I can not make it work with 64ksps. I think 8MHz SPI transmission rate is small. But when you step to 16MHz, I get random data. Do you have any solution to this problem?

    Another question, I am using the internal clock of the ADC, you must connect the CLK pin to DGND or DVDD or can leave floating?


    Greetings,
    Carlos Martins

  • Hey Carlos,

    Let's go through the math:

    The sample period for the 64 kSPS data rate is 1/64,000 = 15.625 us.
    The period of a single 8 MHz SCLK period is 1/8,000,000 = 0.125 us.
    If you collect 4 channels @ 16 bits each + a 24-bit status word, you must shift out a total of 88 bits
    88 bits @ 0.125 us SCLK period comes to 11 us.

    That 11 us MINIMUM possible time for shifting out SCLKs is very close to the MAXIMUM allowable 15.625 us. This means that virtually any delay in SCLK when collecting data from when DRDY deasserts could corrupt conversions. To verify this, look at the scope with one channel on SCLK and DRDY on the other and I think you will see that SCLK takes too long to finish.

    Could you use a frequency between 8 MHz and 16 MHz or does it have to be a multiple? 16 MHz is too fast for the ADS131E04's digital output buffer.

    Regards,
    Brian Pisani
  • Good morning Brian,

    What you're saying is correct. And my problem is even this, my microprocessor work a maximum of 16MHz and it takes a long time to copy the SPI buffer bytes to memory. But when uitlizo a transmission rate 16 MHz SPI is much to ADS131E04. On the other hand, I can not get RDATAC mode 64ksps as an SPI transmission rate to 8MHz. But as the clock source I'm using is 16MHz I can divide by 1 to get the 16MHz and can divide by 2 and get the 8MHz, ie I between 16MHz and 8MHz have no available transmission rate. Probably, if I want to use the RDATAC 64ksps so I have to use a microprocessor to work at 20MHz, the communication rate 8 MHz SPI is enough, because the time between bytes will be much smaller.
    Thank you for your observation.

    In relation to the pins: CLK, GPIO1, GPIO2, GPIO3, GPIO4, OPAMPP, OPAMPN, OPAMPOUT, TESTP and TESTN they are not being used. I connect them to DGND or DVDD or can I leave them floating?

    Thank you very much,
    Carlos Martins
  • Hey Carlos,

    Yes looks like you will need a different microcontroller to shift the data out fast enough.

    The GPIO pins should be grounded if not used. The rest may remain floating.

    Brian
  • Ok Brian, thank you for the clarification. It helped me a lot!

    Greetings,
    Carlos Martins