• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 747 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1248 current input problem

SIVARAMA KUMAR PASUPULETI
Prodigy 160 points
Other Parts Discussed in Thread: ADS1248, CD4052B

Hi,

We are using ADS1248 for current input sensing.

Please find the attached circuit for the reference.

Sample circuit.pdf

The input is applied to CH0_RTD-/TC-/I+ and CH0_V-/I-/RTD- terminals ( Shorting CH0_V+/I+ terminal to CH0_RTD-/TC-/I+).

When we apply 20mA input,

it will flow through the 124Ohm resistor gives a drop of 2.48V.

This voltage is applied to potential divider network (909K and 100K) and the output is around 248mV at the input of CD4052B mux and the same will be given to ADC.

We are setting PGA=8 for taking this close to internal reference. (internal reference is used in this case).

The ADC will give the count according to the (0-20mA) input applied.

After getting the count we are doing calibration to the count.

Calibration: Scaling the ADC raw count to 0 (0mA) to 64000 (20mA) count.

Problem:

  1. When we are applying the input from 0 to 20mA in multiples of 4mA (0mA, 4mA, 8mA,…20mA). We are getting linear count.

  2. When we switch the input from 0 to 20mA the voltage at the input is going above 248mV and taking some time (10 to 15 sec) to stable so the count is fluctuating?

  3. In the circuit maximum RC delay is 1s (10mEG and 0.1MF). So to charge or discharge (with settling) the taken will be 5sec. Then why it is taking 10 to 15 sec of time to settle down. What could be the contribution factor?

  4. When we are switching from 20mA to 0mA, the input at the ADC is going negative and taking same time (10 to 15sec) to settle down to zero.

  5. Through the same channel we are applying the voltage (0 to 10V and -10 to 10V), but we have not observed any problem?

So could you please suggest us what could be the contribution factor for delay? (Whether it is ADC or the RC through which the voltage is not getting discharge/charge properly)?

Also please tell us How to WRITE the driver for this so that we check the driver at our END.

  • 0
    TI__Guru* 92715 points
    Sivarama,


    I'm not sure where the delay is coming from. I don't think this comes from the ADC. However the timescales of the change should make this an easy problem to test.

    Normally, I would have thought that the 10MΩ/0.1uF capacitor combination wouldn't be the dominant RC. You still have an input that comes through about 1MΩ that reacts to the 0.1uF capacitor for both the inputs to the MUX (U7). However, there are some input currents that might be affect the settling. The input currents are dependent on the data rate and are usually in the nA range, so it's unlikely that they would make that much difference.

    There are two things you could do to test the delay. First, you could use an external precision multimeter to measure the voltages at both the input and the reference as they change. If your delay is several seconds, you should be able to see it as it happens. I would measure voltage across C3, C4, C79, and even C82, just to make sure that the voltages change and see how long it takes to settle.

    Second, if you are concerned that the delay comes from input settling, you could start removing external capacitors. C82 should probably remain the same, but the input resistors and capacitors could be replaced with different values.

    I do have one concern. The voltage divider you use is 100kΩ/909kΩ. This means the output impedance of this measurement is rather high (just under 100kΩ). This might cause problems as the input current (or really input impedance) reacts with the measurement's output impedance.

    Out of curiosity, do you have the output data for the measurements that you've taken? I would be interested to see raw data that comes from the ADC. In particular I'd like to see value the inputs and references, what values come out of the ADC, and the consecutive raw data that comes out of the ADC. It would be good to check to see how much it settles from the time of the setting change over the course of 5 to 15 seconds. I'd need to know the data rate to make sure that the output settling does follow some sort of RC time constant settling. Again, I'd want the raw data coming from the ADC (not the value converted to some voltage).


    Joseph Wu
  • 0 in reply to Joseph Wu
    Prodigy 160 points
    Dear Joseph,
    Thanks for the reply. In continuation to the above discussion, I have tried removing the capacitors but in vain.

    I removed 909K resistor. In this case I am getting the required output( no settling time issue when switching from 0 to 20ma and vice versa). But as per our requirement we have to place this resistor for input impedance requirement.

    So please suggest us some other technique to resolve this problem.

    please follow the below procedure for better understanding of circuit.

    1.In the circuit that I shared to you , the follow is the path for current to reach the input of ADC.
    2. I am applying current input from calibrator to CH0_RTD-/TC-/I+ and CH0_V-/I-/RTD- terminals and shorting the CH0_V+/I+ to CH0_RTD-/TC-/I+. ( please refer schematic for the terminal names)
    3. So the current will flow through 124Ohm(R32) resistor.
    4. The voltage developed across the 124Ohm resistor is applied to 909K(R34) and 100K (R35) potential divider.
    5. then it will go to CD4052B MUX input via C4.
    6. Mux output is given to ADC directly (internal reference is used in this case).
  • 0 in reply to SIVARAMA KUMAR PASUPULETI
    Prodigy 160 points
    In continuation to the above conversation, as I am shorting the CH0_V+/I+ to CH0_RTD-/TC-/I+ terminals, my equivalent input impedance will be near to 124Ohm. 909K and 100k should not effect my readings.

    please think on this point also.
  • 0 in reply to SIVARAMA KUMAR PASUPULETI
    TI__Guru* 92715 points
    Sivarama,


    When you remove the 909k resistor, the output settles immediately for the measurement. Did you figure out what capacitance it's reacting with to slow down the settling? I don't see anything on the schematic that would cause that kind of time delay. A small amount of leakage on the X1/X pins of the CD4052 might account for some delay but I don't see anything on the schematic that could cause enough current draw to make a difference.

    Unless you find the source of this delay (which I assume looks like an RC time constant settling), you need to buffer the output of the voltage divider. This would add some op-amp buffer from the junction of R34 and R35. My concern is that you are solving the symptom of a problem but not addressing the cause of it.

    In my previous post, I did ask for some of the raw data coming from the ADC showing the delay might help. I'd need the raw data, with the time information, and the input voltage. Also, I asked you to try to measure the voltages around the input and the reference with a multimeter. Since the delay times are so long, you should be able to see the voltages settle. Just starting with the voltage across R35 should help.

    Do you have a photo or a layout of this board? It might help to get a close-up picture of the ADC and multiplexer to see if there are any other sources of error or leakage.

    Also, is there a reason that you use the CD4052? There are enough multiplexed inputs for the ADS1248 to handle all of the switching for the inputs in this schematic. Other than AIN6 and AIN7, I don't see any other connected inputs. By using the multiplexer in the ADS1248, you might have a simpler schematic, reducing chip count and any potential extra sources of error.

    At this point, it seems as if this problem comes from the input circuitry and not the ADC.


    Joseph Wu