DAC128S085: DAC128S085CIMT

void Spia_init(void)
{
// Initialize core SPIA registers
// - M25P80 Flash at 12.5MHz (75MHz max), rising edge clock
// - CC2500 Radio at 6.25MHz (10MHz max with delays), rising edge clock
// - A3944 FET driver at 6.25MHz (10MHz max with delays), rising edge clock
// - two MCP23S17 I/O at 6.25MHz (10MHz max), rising edge clock
// - two DAC128S085 at 12.5MHz (30MHz max), falling edge clock
SpiaRegs.SPICCR.bit.SPISWRESET = 0; // Set reset low before configuration changes
//SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; // Clock polarity (0 == rising, 1 == falling)
SpiaRegs.SPICCR.bit.CLKPOLARITY = spi_clkpolarity; // Clock polarity CPOL (0 == rising, 1 == falling)
SpiaRegs.SPICCR.bit.SPICHAR = (16-1); // 16-bit character
SpiaRegs.SPICCR.bit.SPILBK = 0; // loop-back (0 == Disable, 1 == Enable)
// SpiaRegs.SPICCR.bit.HS_MODE = 1;

SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; // Enable master (0 == slave, 1 == master)
SpiaRegs.SPICTL.bit.TALK = 1; // Enable transmission (Talk)
SpiaRegs.SPICTL.bit.CLK_PHASE = 1; // Clock phase CPHA (0 == normal, 1 == delayed)
SpiaRegs.SPICTL.bit.SPIINTENA = 0; // SPI interrupts are disabled (non-FIFO mode)
SpiaRegs.SPICTL.bit.OVERRUNINTENA= 0;

SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 7; // Set the baud rate + 1 = even (SPICLK = (200MHz / 4) / BRR)
SpiaRegs.SPIPRI.bit.FREE = 1; // Set FREE bit. Halting on a breakpoint will not halt the SPI

// Initialize SPI FIFO registers
SpiaRegs.SPIFFTX.all = 0xE040; // TX FIFO Reset and enable with interrupts
SpiaRegs.SPIFFRX.all = 0x6041; // Reset flags, RX FIFO Interrupt Enable >= 1 character received
SpiaRegs.SPIFFCT.all = 0x0; // FIFO Transmit Delay between every transfer from FIFO

SpiaRegs.SPICCR.bit.SPISWRESET = 1; // Release the SPI from reset