ADS1194: Precision Data Converters Forum

Hello Gregoire,

Welcome to the E2E forums and thanks for your post!

Your filter capacitor (C19, C21, C23, etc) is quite large. You have a filter cutoff frequency of around ~159Hz which is quite low. This is probably acceptable, but may account for a noticeable reduction in magnitude. Reducing the size of the capacitor may help increase the magnitude at the input of the ADC.

I believe that the majority of the issue is due to the 1Mohm resistor (R15, R16, R18, etc) that provides a path for the signal to ground. When this 1Mohm resistance is in a resistor divider configuration with the 100+Mohm input resistance, the majority of the signal will drive to ground through this 1Mohm resistor. I would recommend removing this resistor.

Hope this helps!

Hi Alexander,

Thanks for the tip !

I tried removing the resistor connected to the ground and it resolved the signal reduction problem. I understand how the signal was lost through the ground path. But is there a way to design an electronic high pass filter that wouldn't lead to this problem ?
For my application, I'm targeting a bandwidth of 0.05Hz - 150 Hz.

Best regards,

Grégoire Germain

Hi Gregoire,

Happy to help!

A couple of questions I have in regards to your design:

1) Why are you using a high pass filter? The RL circuit should filter out a lot of the common DC noise that I think you are concerned about here. You can use a high pass filter, but I would increase the resistance and decrease the capacitance such that you maintain your filter frequency and don't see as large of a decrease in magnitude. Additionally, it is common for low frequency filtering to take place in post processing.

2) What data rate will you be running the device at, and have you considered increasing the bandwidth of your low pass filter? The digital filter will start to roll off at 0.262fDR. If you run the device at 500sps the digital filter will start to roll off at 131Hz, but you will still catch the signals in the 131-150Hz bandwidth. If you operate the device at this data rate then you can increase the low pass filter frequency.

I ask both of these questions because of my concern for the precision of the front end discrete components. If there is a resistance and capacitance mismatch in between P&N lines it can lead to differential input issues. As the value of the discrete components increase, the possible impedance delta increases as well.

Hello!

1) Our goal with the high pass filter is to avoid saturation (>2.4V, <-2.4V) and reduce the baseline wander during small movement and electrode problems. With a filter in post-processing we can address the second issue but not the saturation problem. My understanding was that RL circuit was designed to reject common mode signal (50Hz), does it also have an influence on DC noise ? Thanks for the tip, I'll try using 100 MOhm resistor with 32nF cap.

2) The Data rate I use now is 500 sps but I would like to have the choice to switch to 1000 sps in some cases. But, surely, the low-pass is ineffective in 500 sps configuration.

Thank you for your help

Hi Gregoire,

I see. The RLD creates an inverted common mode signal from the ECG leads of your choosing and will attempt to counter all common-mode interference. Since the DC noise should be common across the ECG leads that you choose to derive the RLD circuit from, it should be countered when it is negatively injected onto the body. Page 58 of the datasheet goes a little more in depth.

You are most welcome.