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ADS131A02: Datasheet errors and general documentation issues/questions

Dave F
Prodigy 60 points
Part Number: ADS131A02
Other Parts Discussed in Thread: ADS131A04

Hi,

I am trying to write FPGA code to talk to the ADS131A02 but even the latest datasheet (RevD Jan2018) seems very unclear and ambiguous in many areas.

1) Table 31 says you have to enable all or none of the ADCs by writing "0000" or "1111" to ENA[3:0] (ie enabling 4 ADCs but does this also apply to the ADS131A02 which only has 2 channels?

2) In dynamic frame mode, at what point does the frame size change.... Datasheet sections 9.5.3.3 and 9.5.3.4 say the ENA[3:0] bits must be cleared/set prior to doing a standby/wakeup command respectfully (note datasheet also incorrectly references ADCx registers regarding enable bits and should reference ADC_ENA register instead) but it is not clear if the reg write command to change ENA[3:0] is what changes the frame size, or if it is the following standby/wakeup command that causes the frame size change.

3) After a reset (soft or hard) it is not clear if you MUST use the null command to retrieve the ready response. I have read somewhere that you can just keep issuing the UNLOCK command until you receive the 0x0655 ACK response to the Unlock command. Is this allowed and/or will it work?... even it it is not 'technically' allowed/recommended.

4) Must the part be unlocked before you can issue a soft reset command?

5) is there any difference between doing a soft reset and just re-writing all the registers to their default values? ie does the soft reset do more than just reset the registers and if so what?

6) Section 9.5.3.10 says "The command status response for the WREGS command is 010a aaaa nnnn nnnn" but the top 3 bits of the WREGS command are "011". ie I was expecting "Ack (WREGS)" as the response ie "011a aaaa nnnn nnnn". Is there a typo in Section 9.5.3.10 ? What is the correct command status response for the WREGS command?

7) Section 9.5.1.2 in Rev D datasheet says "When CRC data integrity is disabled in dynamic-frame mode, the sixth device word for the ADS131A0x is removed from the data frame. If CRC data integrity remains enabled, the device word count remains at six." but Rev C datasheet said "When CRC data integrity is disabled in dynamic frame mode, the sixth device word for the ADS131A04 and the fourth device word for the ADS131A02 are removed from the data frame. If CRC data integrity remains enabled, the device word count remains at six and four, similar to the fixed-frame size option." However, in table 27 (RevD) and table 31 (RevC) the description of the "FIXED" bit is identical. Does the channel count of the device (2 vs 4) affect the frame size in dynamic mode or not? ALSO, Does the channel count of the device (2 vs 4) affect the frame size in fixed mode or not?

8) Do you have any example SPI code available yet?

Thanks

Dave

"

  • 0
    TI__Guru 57366 points

    Hi Dave,

    Thank you for your post and welcome to our forum!

    1. I agree that this is a bit ambiguous. Typically, we don't write to register bits which pertain to channels or features that are not supported in a particular device. I believe you can write 0x0F to the ADC_ENA register anyway and the two bits corresponding to Channel 3 and Channel 4 should be ignored for an ADS131A02 device.
    2. The dynamic frame size takes effect after the ADC_ENA bits are set or cleared, regardless of whether or not the device is later placed in Standby Mode. In other words, you can disable channels without entering Standby Mode, but you cannot enter Standby Mode without first disabling channels. Also you are correct that the "ADCx registers" is a typo - I'll have that added to our backlog of datasheet changes for future revisions. Thanks!
    3. When the device is in a locked state, UNLOCK, NULL, RREG, and RREGS commands are the only four commands which are accepted. I'm not sure what the command status response would be for an UNLOCK command if the device is not ready to accept it. I'll check with our team to see if the device can behave normally if UNLOCK is sent prior to being ready, or if the READY word must come first.
    4. Yes, see answer above.
    5. In addition to resetting register settings back to default, a hard or soft reset will also force the device to re-read the state of the hardware Mx pins and latch them again. This must be done anytime the Mx pins are changed. The device will exit the power-on-reset state in Standby Mode and the interface will be locked. This requires that you unlock the device and wake it up prior to using it again.
    6. I'll confirm this with the team, but Table 13 says the same thing, so I would go by that for now. 
    7. I will also have to confirm this with the team. I expect the register map to be correct (i.e. Table 27 is Rev D).
    8. Sorry, but we do not have example code available for this device.

    Best Regards,

  • 0
    TI__Mastermind 38745 points
    Hello Dave,

    I can add some detail to what Ryan has already provided.

    3) You can continually input the "UNLOCK" command until you get an ack word. The device is not listening until it is ready anyway.

    4) You can issue it, but it will not reset the device.

    6) The table is correct.

    7) The channel count does affect the frame size in dynamic frame mode when channels are enabled. When channels are enabled, the number of channel words correspond to the number of channels. When the channels are disabled in dynamic frame mode, there will be no difference between the ADS131A02 and ADS131A04 in terms of word count. The words will be different in fixed frame mode all the time. In fixed frame mode, the number of words does not change whether the ADCs are enabled or not so the ADS131A04 will have 6 words and the ADS131A04 will have 4 words.

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Prodigy 60 points

    Hi again,

    Thanks for the answers so far but items 1 & 7 are still confusing to me.... and I think item 1 still has not been definitively answered yet....

    The datasheet (table 31 in rev D) seems to say that even for the ADS131A02 2-channel device that I have to enable 4-channels by setting the 4 enable bits to "1111", and, Brian's response above says "When channels are enabled, the number of channel words correspond to the number of channels." So, from the information available it seems that I have to enable 4 channels even though there are only 2 channels and I am worried that these enable bits (for the non-present channels 3&4) may affect the number of words in the reply. Please can you clarify.

    Can you definitively answer please the correct setting of the enable bits (either "1111" or "0011" I guess) for the  2-channel part. Also please can you confirm if these bits affect the number of words in dynamic mode, or is the number of words 'hard-coded' internally in the 2 vs 4 channel devices.

    Lastly, ref the enable bits and comments in table 31....is it really not possible to enable just the ADC channels required. e.g. just enable 1 channel of a 2 channel device?

    Thanks

    Dave

     

  • 0 in reply to Dave F
    TI__Mastermind 38745 points

    Hey Dave,

    Sorry for not being more clear. It is fine to write either '0011' or '1111' to the enable register of the ADS131A02. The result will be the same: two data words. The number of words is "hard-coded" as you say. In fixed-frame mode for the ADS131A02, the data will have 4 output words independent of whether the channels are enabled or the CRC is on.

    To answer your final inquiry, yes it is true. You must enable all or none of the channels i.e. both channels of a two channel device must be enabled and disabled simultaneously.

    Brian

  • 0 in reply to Brian Pisani
    Prodigy 60 points

    Thanks very much Brian & Ryan for all the answers.

    Best regards

    Dave