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Hello Everybody,
i'm trying to get the serial interface of the ADS7952 to work with the SPI of a AT91SAM9 (ARM 9), but the ADS7952 is behaving very unexpectedly.
I'm sending the following data words:
while(1)
{
0x4200 // device reset
for(i=0;i<3;i++)
0x1080 //manual mode, channel 1
}
Here is a screenshot of the SPI transfer:
MISO is the SDO line; MOSI is the SDI line; clock rate is ~350kHz, AREFP is 3.0V, +VA is 3.3V, +VB is +3.3V
If i shift the clock 1/2 period, so that the rising edge of the clock and the rising edge of the data bits are simultaneous, the ADS7952 output word is the channel number and the sample data. Although the channel selected by the ADS792 is not the channel i programmed, the sampled data is correct (i applied 1.5V to channel 8 and GND to all other channels). Here is the screenshot:
Schematic for reference (what you can't see: the NC pins are tied to GND)
I assume i am doing something wrong with the SPI timing, but as far as i can see my timing complies the timing requirements from the datasheet.
So i would appreciate any suggestion that helps me to get it work.
Best regards
Paul Roßmann
Hi Tom,
first i connected the SPI wires from the ARM board directly to the ADC3 thereby detaching all other devices from the bus. After that i took the screenshots, and it looks much better now. Order of screenshots is: slave side complete cycle, slave side zoomed, then master side complete cycle and at last master side zoomed.
The ADS7952 switches to the desired channel in frame 4 (i would say one framt to late, but that may be relatet to the device reset) and samples the correct data. I'm going to attach the other device to verify that there is the problem.
Best regards,
Paul
Hi Tom,
i found the source of the problem (at least i think i found it):
if i connect the SPI wires from the ARM board to the SPI bus on my board (and not directly to the ADC3_SPI connector block), there is a lot of ringing and crosstalk going on. If i connect the SPI wires directly there is ringing to, but it is reduced by 1/2. The voltage spikes on the SDI line at the rising edges of the clock are about +-920mV. With 3.3V supply the lower bound of the logic high level voltage with 0,7*3.3V = 2.31V is close to this. With the direct connection the spikes are +- 480mV.
I assume the reason for this is my board layout. The clock and SDI lines are placed directly next to each other, without any ground plane for shielding (it is my first layout with any fast digital signals, and a quite dense layout too).
It would be nice if you could confirms my assumtion.
To continue prototyping with my board i thinksimple rewiring the spi with loose wire should be sufficient.
Best regards and thanks for your help, i'm going to bed now (00:19 am in Germany now)
Paul Roßmann
