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DSS openSession

Robson Tovo
Prodigy 120 points

I'm writing some automation scripts that use DSS to communicate with my target. 

So, I have to call DSS externally. Every time I open a session, it takes 5 seconds: 

ds.openSession( "Blackhawk XDS560v2-USB Mezzanine Emulator/C66xx_0" )

and the console shows the message: 

Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc

Is the probe really loading the FPGA every time I open a session? Is this causing the observed delay?

I need this script to run faster, because there are thousands of test cases to run on the target.

Any help?

Thanks.

  • 0
    TI__Guru**** 168894 points

    Hi,

    I think 5 seconds is a pretty quick time to launch a debug session with a XDS560v2 on a C66x device, especially if you are opening multiple cores and running GEL files.

    Even still, I would suggest a few tips:

    - If you are connecting using a GEL file, usually any calls to GEL_TextOut() take some small extra time to run.

    - Set the TCLK speed to a fixed, known good value (start with 10.368MHz). From inside the target configuration editor, select the tab Advanced and set the option as shown below:

    - Try to connect to a smaller number of cores (if more than one) or create a custom configuration bypassing all the cores you do not use. This tends to speed up the connection.

    - Try to optimize the scripts to do more without having to relaunch the debugger. Sometimes a restart or reset go a long way when testing different things

    These are the ideas we have at this moment, but I will reply to this thread if I have something else to add.

    Regards,

    Rafael

  • 0 in reply to desouza
    Prodigy 120 points

    desouza said:

    Hi,

    I think 5 seconds is a pretty quick time to launch a debug session with a XDS560v2 on a C66x device, especially if you are opening multiple cores and running GEL files.

    5 secs is too much for my case. I'm not using GEL, and only a single core from C6678. Specially when comparing to the other 2 target boards we have here for other processors (not TI). They take no time to connect to the probe and issue commands to the target.

    Again, I have an external application that sends data to the target and reads data back. Each test case has hundreds of steps, and each step calls a DSS javascript to run. 5 secs for each call to DSS is way too long. I confirmed that the script line that takes longer is the call to openSession().

    desouza said:

    Even still, I would suggest a few tips:

    - If you are connecting using a GEL file, usually any calls to GEL_TextOut() take some small extra time to run.

    I'm not using GEL.

    desouza said:

    - Set the TCLK speed to a fixed, known good value (start with 10.368MHz). From inside the target configuration editor, select the tab Advanced and set the option as shown below:

    Where do I access the Target configuration editor? Does this change saves to the .ccxml file?

    desouza said:

    - Try to connect to a smaller number of cores (if more than one) or create a custom configuration bypassing all the cores you do not use. This tends to speed up the connection.

    How do I create a configuration to bypass all the cores I don't use? Opening a session just to Blackhawk XDS560v2-USB Mezzanine Emulator/C66xx_0 is enough?

    desouza said:

    - Try to optimize the scripts to do more without having to relaunch the debugger. Sometimes a restart or reset go a long way when testing different things

    Already doing this. There is just a dss call to load the program to target and the other dss calls write to target, runs and reads back data.

    desouza said:

    These are the ideas we have at this moment, but I will reply to this thread if I have something else to add.

    Regards,

    Rafael

    Thanks. Apreciate that. 

  • 0 in reply to Robson Tovo
    TI__Guru**** 168894 points

    Robson,

    Robson Tovo said:
    Where do I access the Target configuration editor? Does this change saves to the .ccxml file?

    From inside CCS, you can simply double-click on any .ccxml file and it opens the target configuration editor. Any changes to it will be saved to the .ccxml.

    Robson Tovo said:
    How do I create a configuration to bypass all the cores I don't use?

    Check: http://processors.wiki.ti.com/index.php/Multi-Core_Debug_with_CCSv5#Debug_Configurations

    You can also modify the .ccxml file in the target configuration editor and set all the other C66x cores to "Bypass".

    Hope this helps,

    Rafael

  • 0 in reply to desouza
    Prodigy 120 points

    Increasing the JTAG clock and bypassing the other cores speeded up the process, but is still too long (~5 sec/call). 

    I will try now the TestServer.js (one examples script on TI installation folder) . I think this will solve my problem with timing, since once the debugger session is opened, the other operations execute pretty fast.