TINA/Spice/TLC2262: Some questions about TINA simulation in transient analysis and AC analysis

Hello Haoyang,

The current op amp configuration (Vin=500mV and f=500kHz) is operated above its slew rate limit. So I think this is the reason behind the transient behavior of the model.

The slew rate value of the op amp TLC2262 is 0.5 V/us.

SLEW RATE= 2 * PI * f * V.

Where

     f = the highest signal frequency, Hz

     V = the maximum peak voltage of the signal.

For the current model, depending upon the slew rate limit, the highest signal frequency would be approx. 160kHz.

• As an example, take the scenario where an op amp is configured with a signal with a peak amplitude of 500m volts at a frequency of 250kHz

As can be seen in the diagram, in the limit, the op amp slewing distortion will result in the creation of a triangular waveform. If the frequency is increased further the op amp will be even less able to keep up and therefore the amplitude of the output waveform will decrease.

Regards,

Aditya C

Hi Haoyang,

Please find the answers below,

1. As per datasheet, the ADC is unipolar, so it can convert A-to-D (i.e. give digital bits) for voltages > 0 to Avdd.

But, the ADS7046 model captures the SHA circuitry, and gives out the sampled value as the output.

As I can see from simulation no clamping for <0V is implemented in the SHA model output, so it can sample values <0V in the input correctly, as well. So sampled output will also be seen correct.

But the real ADC will not give correct output bits for -0.5V.

2. Avdd should be always connected to 3.3V as per datasheet for typical operation.

From the simulation it seems that some clamping logic has been implemented on the positive ceiling of sampled output, depending on Avdd input voltage such that, it can reach a max of, ( Avdd- some headroom value)

That is the reason I think you could see sampling time getting elongated when Avdd and input voltage value is set nearby, because some other circuit is trying to limit the output at that time.

3.On the sampling frequency front, the effect will be seen via settling time/ setting voltage error value.

The spec of maximum frequency is derived from the settling time of the sampling cap needed.

The bandwidth of the switch in Typical condition is designed accordingly (with some 20-30%  margin, ie if requirement is 3MHz, say it will be designed for %MHz in Typical)such that it meets the settling time across corner.

Also in real design the resistance is a MOSFET so its parameters varies as with Vin, but in model we ususally have a fixed typical resistance and cap value.

So this will serve correctly in model, even for some higher frequency than 3MHZ. After that with eventual increase of frequency, we will see that the sampling cap will be unable to track and settle so fast, so there will be more error in the sampled voltage value; or in other words it will not be able to settle to the desired value in that time frame.