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TMS320C6678ACYP(2.0) PCIE boot

xiao wu
Prodigy 30 points

Hi,

    we have Revision 2.0 of the Si now.

    we laod the code by pcie,but it can not boot(situation same as  1.0 Si).

   when  the code is loaded  completed,then write the start address to magic address. but the 6678 can't boot.

   we moved  PC pointer  to start address by Emulator ,then it can boot(it's mean the code is ok)

My question is : if the Revision 2.0 of the Si can boot from PCIE not use EEPROM?

My PCIE boot configure as bellow(Please check it):

our device status register value：0x00015809


LENDIAN＝1           System is operating in Little Endian mode
BOOT[2:0]=100       (PCI)
BOOT[8:5]=0000       32bit
BOOT[12:10]=011      100M
BOOT9,BOOT4,BOOT3Reserved =>0

PCIESSEN=1           1 = PCIe module enabled
PCIESSMODE[1:0]=01   PCIe in Legacy End-point mode (support for legacy INTx)
PACLKSEL=0           Selects CORECLK(P/N)

BR

wuxiao

  • 0
    TI__Genius 9915 points

    Do you have a Shannon 2.0 EVM? We have confirmed that the PCIe works in the new Shannon2.0. But we are yet to confirm the PCIe boot. Please let me know your setup.

    Thanks,

    Arun.

  • 0 in reply to ArunMani
    TI__Expert 8670 points

    Arun,

    The setup was shown as the above post. And they just used the mcsdk_2_00_04_16\tools\boot_loader\examples\pcie\linux_host_loader for test. Would you pls try it and feedback ASAP?

    Thank you very much.

  • 0 in reply to Andy Yin
    Intellectual 830 points

    If you want to boot over PCIe with R2.0 silicon without using the EEPROM PLL workaround, then the boot proceedure is slightly different.

    After writing the boot magic address for core 0, you must send an interrupt to core 0.

    In my setup, I send an MSI interrupt to address 0x21800054 with MSI data 0x00000000. Since you are using legacy INTx instead of MSI interrupts, you should do INTx equivalent.

    If you send the interrupt before writing the boot magic address, the boot will lock up and not respond to any further interrupts.

    The above was not clear in the documents, although Edition A of SPRUGY5 slightly hinted at it.

    With the PPL workaround, the C6678 sits in a loop polling the boot magic address, but with R2.0 (no EEPROM workaround) the C6678 executes IDLE instruction.

    I wish TI would update the mcsdk_2_00_XX_XX\tools\boot_loader\examples\pcie\linux_host_loader to include this needed change.

  • 0 in reply to Jonathan White
    TI__Expert 8670 points

    Jonathan,

    I am not clear with the "After writing the boot magic address for core 0, you must send an interrupt to core 0." . Do you mean the application executed in core0 needs to send an interrupt to the core0? But how to make the core0 run the application?

    Thanks.

  • 0 in reply to Andy Yin
    Intellectual 830 points

    Andy, with the R2.0 silicon (and no EEPROM PLL workaround) the external host downloader must write the boot magic address for Core 0 then write to the MSI interrupt register (over PCIe) to boot core 0. The application will then start in core 0. It is the external PCIe host loader that writes the code, the magic address, and the MSI register poke, all over PCIe

    The above was not needed in R1.0 with EEPROM workaround. See SPRUGY5A Page 3-11, although the text their is unclear and possibly inaccurate.

    But I do know the MSI is needed from tests I've done.

  • 0 in reply to Jonathan White
    TI__Expert 8670 points

    Jonathan,

    Got it, thank you very much for your clear explanation.

    B&R

  • 0 in reply to Jonathan White
    Prodigy 30 points

    Dear Jonathan:

    thank you very much

    I have resolved this problem by jonathan said above.

    hardware configure as below:

    LENDIAN＝1           System is operating in Little Endian mode
    BOOT[2:0]=100       (PCI)
    BOOT[8:5]=0000       32bit
    BOOT[12:10]=011      100M
    BOOT9,BOOT4,BOOT3Reserved =>1

    PCIESSEN=1           1 = PCIe module enabled
    PCIESSMODE[1:0]=00  PCIe in  End-point mode

    PACLKSEL=0           Selects CORECLK(P/N)

    by the way,i found PG1.0 can aslo boot from pcie without EEPROM PLL workaround,the way same as PG2.0 prosess above.

    BR

    wuxiao

     

  • 0 in reply to xiao wu
    TI__Expert 8670 points

    Xiao,

    Did you just change the below code? 

    PCIESSMODE[1:0]=00  PCIe in  End-point mode

    Would you pls share your email address for me?

    Thanks.