Hi,
I have a board with a RGMII Broadcom PHY and I'd like to boot off the network using it. I've successfully booted the EVM over the network only when connected to a 100 Mbps switch or hub.
My problem arises with two issues:
1) The GTXCLK internal delay for my RGMII Broadcom PHY is enabled by default. So is the GTXCLK internal delay on the EMAC. This creates too much clock skew at 1 Gbps as the extra 1.9ns delay @ 125 MHz creates about 24% error. Is there a way to disable this on the TI part that is not documented? Maybe a sysboot pin? I've noticed that sysboot[7:6] aren't documented. This is mostly wishful thinking and an enhancement suggestion. I've checked that there is no way to set this on my PHY out of reset other then the MDIO interface.
2) Since the internal delay is turned on, I'm forced to boot at 100 Mbps where the RGMII GTXCLK is turned down to 25 MHz and the clock skew is tolerable. I've studied the boot ROM assembly extensively and the boot ROM appears not handle the auto negotiated settings at all. It reads the PHY's BMCR (0x0) register and then uses those settings to configure the SL1_MACCONTROL/RGMII interface and proceeds on. The problem is that my PHY comes up with the BMCR set to 0x1140 for 1 Gbps, the Boot ROM reads this and then sets RGMII to operate at 1 Gbps mode and sets the RGMII GTXCLK to 125 MHz which doesn't work due to (1) above. On the TI8148 EVM, the Boot ROM reads the BMCR register as 0x3100 which is 100 Mbps (despite being plugged into 1 Gbps or 100 Mbps hub/switch). It then sets the SL1_MACCONTROL/RGMII to operate at 100 Mbps which is the 25 MHz GTXCLK I'm looking for.
Can somebody confirm that this is infact the way it works? It would seem that reading the Phy's Auto Negotiated Link Partner Ability register and setting the SL1_MACCONTROL register accordingly would make the most sense. This would allow my board to boot. This would probably also enable the EVM to boot on a 1 Gbps switch.
The TRM states "Reads the CONTROL register to detect the auto-negotiated mode of operation" which does correctly state what the Boot ROM does in fact do. From my understanding of the MII interface the Boot ROM should be reading the LPA (Link Partner Ability) register to successfully use the auto negotiated settings to set the SL1_MACCONTROL. This seems like a Boot ROM silicon bug.
On a side note, I can confirm that (1) and (2) are happening because if I disable the internal delay using JTAG the board boots just fine on a 1 Gbps switch, and if I override the SL1_MACCONTROL register using JTAG the board boots just fine at 100 Mbps.
Any insight?
