AM389/7x GPIO Toggle rate

Hi Marc,

What ever the values (0/1) we are writing to the GPIO registers will effect on the IO pins after some hardware latency. And toggling of 1->0 or 0->1 is dependent on rise time and fall time of the IO pins.

Unless untill we know those values we can't say a specific toggle rate.

Regards

AnilKumar

Anil,

So if i understand your statement correctly we can change the value of the GPIO registers on every clock cycle. There is no limitation built into the architecture on this. It is just a matter of delay to the IO pins. This results in a few additional question

• Is the Functional clock to the GPIO registers the same as the ARM core frequency?
• Do we have any information on the latencies of the chip package for Gpio? Which could tell me the maximum theoretical effective toggle rate (to the outside of the package)
• Do you have some example latencies from the EVMs? Which could tell me a ballpark maximum using real hardware

Thank you for your help,

-Marc

Thanks Anil! 

I appreciate the quick response.