"Skew Length Mismatch" in OMAP-L138 Datasheet

See in line below notated by [MS].

Hi,

In section 5.11.3.11 on page 136, Table 5-36, row 2, the following line can be found:

"CK A to B/A to C Skew Length Mismatch-------------------- MAX: 25 Mils"

1. What in the world is "skew length mismatch"? I'm sorry, I'm fairly new to PCB design, and I asked about 10 professors from my own and other relevant institutes, and no one could provide me with an exact answer.

 I mean, the most intuitive interpretation  would be: "The CLKP and CLKN signal routes should not vary more than 25mils in length", but I really don't know if that's a correct interpretation because it does not try to explain what in the world "CK A to B/A to C" is supposed to mean.

[MS] There is a figure that defines the endpoint and the segments.  The route is a balanced "T" starting with the DSP at point A, going through segment A, and branching into a T to reach endpoints B and C via segments B and C, respectively.   This is shown in the data sheet in Figure 5-23.  The spec for this routing is in Table 5-36.

Your intuitive interpretation is correct.  The intent is to keep the lengths of CK and CK# within 25 mils of each other.  

"skew" is an extremely common term meaning the differences between net lengths.  It is used by PCB professionals who actually design boards in the real world, rather than academia.  I recommend consulting with PCB board shops and/or those who train PCB designers rather than electrical engineers.

2. I don't even have two DDR2 ICs, only one, so that entire balanced T thing is not really applicable in my case. Any thoughts?

[MS] It's perfectly applicable, just drop off the leg of the T you are not using.  C goes away and you are left with just A and B, a straight line trace.  The specs in Table 5-36 still apply. 

3. What exactly is the datasheet talking about when referring to "segments". If I only have one DDR2 IC, and only segment A and B aplies, then does that mean I can only have ONE turn/corner for that exact signal route? Because if I have more corners, then I'd have more than two segments..no?

[MS] Unless you get into really high GHz stuff, electrical signals don't know they have turned a corner. 

4. What is meant by "nominal trace length" on row 5? I understand "trace length" but not when it has an added "nominal" before it.

[MS] It is the nominal trace length.  More simply put, it is the average trace length.  Recall that all the traces are matched together in the CK and ADDR_CTRL net classes, thus they will have a nominal length and a skew of up to 100 mils.

5. On row 1 the Datasheet is referring to CK-CKN.. Correct me if I'm wrong, but CK is a signal net CLASS that consists of PIN NAMES DDR_CLKP and DDR_CLKN(active low). So, according to those definitions, when I see "CK-CKN" I automatically assume that there is ANOTHER CLASS called CKN, since CK is a class. Then when I don't find it I get frustrated. Is the Datasheet trying to refer to the signals running out of the DDR_CLKP and DDR_CLKN pins? In that case why is it not consistent? Seriously, consistency in documents like these should be treated with high importance. You can't just pull out a "CKN" out of nowhere and expect people(beginners) not to be confused. Or is incosistent labeling like this just a part of the game within this field? Or is the standard just to not annotate the Positive signal in a class consisting of only two signals, and just use the entire class name for the positive signal? That is not a very impressive standard.

[MS] The term "CK" means different things in different contexts.  Yes, it is a net class containing the nets CK and CKN (or CK#).  It is also a signal.  If used generally, it means the pair CK and CKN.  If used specifically, it means CK only, independent of CKN.  Sometimes the non-inverting CK signal is referred to as CKP just to be more specific. 

 Sorry for the tone on Q5, just a bit of frustration I needed to get out :)

Anyway, I'd appreciate any help I can get on this. Thanks in advance!

 [MS] The tone does not help.  You are having difficulty due to this being new to you.  There is no harm with asking the questions but hitting up your more experienced peers with "tone" will just turn them off.

If your background is engineering I'm sure you will find PCB layout very different from what you were expecting.  I know I did.  PCB layout is a blend of mechanical engineering with a whole bunch of "graphic artist" thrown in and it is a profession in and of itself.  The DDR layout spec for the OMAP-L13x is written for PCB layout professionals who understand the terminology.  PCB layout guys speak a different language than electrical engineers and it takes some effort to be able to relate across the professional lines.

If you are actually going to layout and build a system, my advice is to get the PCB layout shop involved now and get their advice.  If you are going to do it, then this will be a great learning experience, but it will be quite challenging and likely frustrating.   The terminology isn't too bad, but the tools are some of the most unintuitive conceived by man.

 -Mike