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ISO3082: IEC61000-4-6 RS485 ISO3082DWR

Part Number: ISO3082

Hello,TI engineer,When I did the IEC61000-4-6 test on the 485 interface (10V 150K~80Mhz), there was interference on the 485 signal line. The communication method adopts self-loopback. For example, RS485-1 channel and RS485-2 channel loopback communication.

During the test, it is judged whether the communication is normal by watching the signal light on or off. If the communication is interrupted, the signal light will be on; if the communication is normal, the signal light will not light. However, the observed waveform at the 485 AB end is now disturbed, as shown in the following figure.

the rx tx signal which connect to FPGA is not Not affected。Does this situation indicate that my RS485 can withstand the IEC61000-4-6 test?OR  NOT?Where do I need to improve?

  • Dear User,

    Thanks for using our E2E forums.

    Per common standards and practice, are you injecting this -4-6 waveform to both A and B pins? If so, this is expected.
    RS485 is a differential signalling protocol as you may already be aware, so the receiver inside the chip is designed to respond only to the differential component of the signal and then reject noise that is common to both A and B lines. (often called CMR or common mode rejection for short). This is applicable for both common mode shift on the lines (DC) and transient/AC events like the tests you have done. No system will have infinite or perfect CMR of course, but finite CM rejection will be there. This is why the RX (Receiver) output is still OK.

    With all this said, please note that we don't have a formal spec or guarantee in the datasheet for this, since the result depends also on the system, layout , matching of external components etc. But what this does tell us is that this system setup used for this test is reasonably good for this test.

    Hope this helps!
    Please let us know if you have further questions.