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  • Resolved

ISO7740: External Circuit needed to keep ISO7740F from glitching on power-up

Expert 4925 points
Steve Widener

Replies: 8

Views: 375

Part Number: ISO7740

The output of the ISO7740F is listed as "Undetermined" in table 2 of the datasheet when Vcco < 2.25V.

Is there any way to arrange the device (perhaps with external components) so that there is no glitch (going high) when Vcco is applied? (assume EN is held low and Vcci may be powered down or powered up with input Low)

Expert 4925 points
Steve Widener
  • Expert 4470 points
    Manuel Chavez
    Hi Steve,

    The ISO7740F keeps output pins low when input signals or Vcci are lost, so this is the right part for preventing the output from going high undesirably. To add a layer of security that the output will be low during conditions described above, a 100kOhm - 1MOhm pull-down resistor can be added to the output.

    Please let us know if this is helpful!


    Thank you for posting to the E2E forums,
    Manuel Chavez
  • Expert 4925 points
    Steve Widener

    In reply to Manuel Chavez:

    Thanks Manuel !

    Is this true even if Vcco is < 2.25V? this seems to contradict the datasheet guidance.
  • Expert 4470 points
    Manuel Chavez

    In reply to Steve Widener:

    Steve,

    You're welcome! The datasheet table doesn't cover cases with external components, like pull-down or pull-up resistors. The addition of a pull-down connects the output path to ground even if the voltage on the output pin is indeterminable.

    What amplitude and duration are the glitches we're looking to prevent? Bench testing on the previously mentioned table condition shows voltage on the output pin to be 300mV or less during the moment of startup and on the timing order of microseconds and nanoseconds as shown in the following picture. These amplitudes are not expected to turn on any external components since they are lower than most thresholds.



    I will await your response.


    Thank you,
    Manuel Chavez

    P.S. Post was text was edited for clarity

  • Expert 4925 points
    Steve Widener

    In reply to Manuel Chavez:

    Thanks Manuel!

    The basic requirement is to keep a MOSFET gate from switching. The threshold voltage is ~ 1.1V so if we are less than, say 650mV, that may be adequate. The test data looks promising but it is not clear from the data provided that the output is guaranteed to stay below 650mV with different dv/dt of the Vcc2 rail or across PVT. I guess the issue is that we state the output is "indeterminable" and that could be understood to mean that the output could drive high with Vcc2 < 2.25V. If that's not the case, please let us know. The operation needs to be guaranteed as this is a very critical application.

    The alternative we have recommended is to use a separate TPS3106-EP supervisor to keep the FET off when 0.4< Vcc2 < 2.25V. That device is rated for operation at low voltages.
  • Expert 4470 points
    Manuel Chavez

    In reply to Steve Widener:

    You're welcome, Steve!

    Thanks for the details in this response. High outputs are not expected on the ISO7740F outside of data transfers, but please give me 2-3 days to check out the voltage supervisor and verify with the isolation team. Insights to the questions below will be helpful meanwhile.

    When is Vcco expected to be lower than 2.25V?
    What is the turn-on time of the FETs?


    Respectfully,
    Manuel Chavez

  • Expert 4925 points
    Steve Widener

    In reply to Manuel Chavez:

    The FET could turn on in the 10-20nsec range
    Vcco could be lower than 2.25V on power-up or down, independent of the state of Vcci
  • Expert 4470 points
    Manuel Chavez

    In reply to Steve Widener:

    Hi Steve,

    The waveform attached in a previous post was captured during powerup, but since then I have not been able to reproduce it in the lab to test out our proposed solutions. Wiggles on the output vary based on device-to-device variations as well as the PCB environment the ISO7740F is in. Our team suggests using a 10kOhm pulldown resistor on the output pin to help reduce voltage waves and adding a small capacitor of ~0.1nF in parallel can help reduce any voltage wiggles even further. The supervisor IC is a valid solution, it just may be overkill.

    We can continue testing to check if these solutions are good; please let me know if you or our customer would like us to proceed.


    Have a good weekend!
    Manuel Chavez

  • Expert 4925 points
    Steve Widener

    In reply to Manuel Chavez:

    Thanks Miguel - even through the supervisor is overkill, it is guaranteed by traceable specifications. We'll recommend that approach.

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