I am seeing a latch up condition on the Vcc pin of the logic gate. To recover we have to toggle the inputs or just probe the Vcc or output pin with multi-meter.
We power the logic gate Vcc through a 4.75kohm resistor. We have a delay circuit to hold off the Vcc to the logic gate by pulling it down for 120ms before releasing it. During the 120ms we have applied voltage ~2v on output pin. One of the inputs is pulled high to 3.3V by 4.75kohm. The reason for the output pin ~2v is that it's going through an opto diode/resistor from 3.3V. After releasing the 120ms delay the Vcc pin gets latched at ~400mV and thus it can't drive the output. To recover we just toggle one of the inputs.
When we placed a 74LVC part in same circuit we see no latch up issue. Only the 74AUP gets latched up. Multiple boards were used and same behavior.
Based on the datasheet for Ioff it states that during power down mode there should be no back feeding to the device for both the 74LVC and 74AUP. Puzzled why 74LVC doesn't latch up?
Is there any major difference between the two parts that would cause one to latch up and not the other? Can we say with confidence that 74LVC won't latch up and we are not marginal in both cases and just happened to see it on the AUP part?
