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uart_echo plus HCT_example causes conflict

I am trying to merge the hct_example.c code for the Concerto PLC eval unit with the uart_echo.c example. The former uses a software interrupt to access the ipc.and the latter uses a hardware interrupt to service the uart0 port. Both work fine independently (running their seperate demo programs). But when I try to combine the functionality, the application hangs. I am also running FreeRTOS. When I assign a task to just service the uart0 port, that seems to work, but I'm not sure how reliabiy, so I would like to collect serial information via interrupts. I plan to use a circular buffer. Any ideas as to why I have this conflict?

THanks,

Pat

 

4 Replies

  • As addendum, here is my config setup:

    void
    Config_c28x(void)
    {
      // Disable Protection
      HWREG(SYSCTL_MWRALLOW) =  0xA5A5A5A5;

      // Setup main clock tree for 75MHz - M3 and 150MHz - C28x
      SysCtlClockConfigSet(SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_2 | SYSCTL_USE_PLL |
                           (SYSCTL_SPLLIMULT_M & 0x0F));
      // enable serial uart port 0
      SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
      
      // Enable all GPIOs
      SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
      SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
      SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
      SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
      SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
      SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
      SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
      SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
      SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
     

      //    /* pull up for ECAP */
      GPIOPadConfigSet(GPIO_PORTB_BASE, 0x0A, GPIO_PIN_TYPE_STD_WPU);
      //
      //    /* pull up for McBSP-A */
      GPIOPadConfigSet(GPIO_PORTD_BASE, 0x70, GPIO_PIN_TYPE_STD_WPU);
      //   
      //    /* pull up for UART */
      GPIOPadConfigSet(GPIO_PORTE_BASE, 0x30, GPIO_PIN_TYPE_STD_WPU);
    // from echo demo
        // Enable processor interrupts.
        IntMasterEnable();

        // Set GPIO E4 and E5 as UART pins.
        GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_4 | GPIO_PIN_5);
        GPIOPinConfigure(GPIO_PE4_U0RX);
        GPIOPinConfigure(GPIO_PE5_U0TX);

        // Configure the UART for 115,200, 8-N-1 operation.
        UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(SYSTEM_CLOCK_SPEED), 115200,
                            (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
                             UART_CONFIG_PAR_NONE));

        // Enable the UART interrupt.
        IntRegister(INT_UART0, UARTIntHandler);
        IntEnable(INT_UART0);
        UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);

      // a "1" gives C28 control of GPIO bits, "0" gives CM3 control
      // PC6&7 - LED2 and LED3 on Concerto card, PH3 & PF2 - LD4&5 on docking station,
      // and PB0, PA6&7 (AFED1,2,3 on AFE board) are config to CM3   
      GPIOPinConfigureCoreSelect(GPIO_PORTA_BASE, 0x3F, GPIO_PIN_C_CORE_SELECT);
      GPIOPinConfigureCoreSelect(GPIO_PORTB_BASE, 0xFE, GPIO_PIN_C_CORE_SELECT);
      GPIOPinConfigureCoreSelect(GPIO_PORTC_BASE, 0x3F, GPIO_PIN_C_CORE_SELECT);
      GPIOPinConfigureCoreSelect(GPIO_PORTF_BASE, 0xFB, GPIO_PIN_C_CORE_SELECT);
      GPIOPinConfigureCoreSelect(GPIO_PORTH_BASE, 0xF7, GPIO_PIN_C_CORE_SELECT);
      GPIOPinConfigureCoreSelect(GPIO_PORTE_BASE, 0xCF, GPIO_PIN_C_CORE_SELECT);

      GPIOPinConfigureCoreSelect(GPIO_PORTD_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);
      GPIOPinConfigureCoreSelect(GPIO_PORTG_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);
      GPIOPinConfigureCoreSelect(GPIO_PORTJ_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);


      // Copy time critical code and Flash setup code to RAM
      // This includes the following ISR functions: Timer0IntHandler(), Timer1IntHandler()
      //  and InitFlash();
      // The  RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart
      // symbols are created by the linker. Refer to the device .cmd file.

      MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);

      // Call Flash Initialization to setup flash waitstates
      // This function must reside in RAM
      FlashInit();

      // Enable processor interrupts.
      //IntMasterEnable();

      // assign S0 to S7 of the shared ram for use by the c28 PLC
      RamMReqSharedMemAccess((S0_ACCESS | S1_ACCESS | S2_ACCESS | S3_ACCESS | S4_ACCESS | S5_ACCESS | S6_ACCESS | S7_ACCESS),SX_C28MASTER);

      // WKIM: in case of debugging, enable this routine
    #if 1
      // check if the RAM is init
      // we use the C2M MSG RAM as indication
      // the magic data: 0xdeadbeef
      if (c28_init == 1)
      {
        return;
      }
    #endif

      // wait for c28 initialization
      master_ram_init_control_m1_msgram_memories();
      master_ram_init_control_L0_L4_memories();

      // C28 boot from flash
      IPCMtoCBootControlSystem(CBROM_MTOC_BOOTMODE_BOOT_FROM_FLASH);


    }

     

  • In reply to Pat Harris:

    Again, here is the specific code. This appears to conflict with a SWI or something. It's the last line that, when not commented out, will cause the program to hang.

    Can anypne provide guidance here?

    Thanks

     //    /* pull up for UART */  

     GPIOPadConfigSet(GPIO_PORTE_BASE, 0x30, GPIO_PIN_TYPE_STD_WPU); // from echo demo    

     // Enable processor interrupts.    

     IntMasterEnable();

        // Set GPIO E4 and E5 as UART pins.    

     GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_4 | GPIO_PIN_5);    

     GPIOPinConfigure(GPIO_PE4_U0RX);    

    GPIOPinConfigure(GPIO_PE5_U0TX);

        // Configure the UART for 115,200, 8-N-1 operation.    

    UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(SYSTEM_CLOCK_SPEED), 115200,                       

      (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |        UART_CONFIG_PAR_NONE));

        // Enable the UART interrupt.    

     IntRegister(INT_UART0, UARTIntHandler);    

     IntEnable(INT_UART0);    

     UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);

  • In reply to Pat Harris:

    Are you still running into issues here or did you manage to resolve this?

  • In reply to BrandonAzbell:

    Brandon,

    Yes, I did resolve the problem, thanks,

    Pat