Hello Guys,
I'm using the F2812 in a multi processor system and the communication is done over SPI where the F2812 acts as slave. I need to ensure that the shift register will be resynchronized if the sync is lost. As I'm using codes with a hamming distance of 5 for the transmission, I can detect sync problems easily. So in the case an invalid word is received I just need to reset the receive channel and the bit counter. But it seems that the counter isn't resetted by just writing 0 to SPIRST. So at the moment only resetting the CPU resynchronizes the SPI in case of sync problems.
Any idea how to clear the bit counter by software?
Regards
Peter