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What are the CPU speed to execute code in flash for the F280x devices before the device is initialized?

Yanming Luo
Guru** 111090 points

Champs,

Refer to datasheet and user guide of C28x, the flash pipeline mode is not active, flash paged/random read wait states need 15 wait states and a total of 16 sysclock cycles per access the flash code/data after device reset or power up. There are serveral question on these.

1. What are the minimum CPU speed to execute code in flash for the F280x devices when device power up or after reset before the device is initialzed? ( The crystal attached to the 280x devices is 20MHz)

2. Do pagewait or randomwait register affect the flash access speed if the flash pipeline mode is not active? (ENPIPE=0)

3. What the flash access speed will be if the flash pipeline mode is no active and sysclock is 10MHz?

  • 0
    TI__Expert 8500 points

    Yanming,

    1) Since the pipeline mode is not enabled, each access (16-bit or 32-bit) will be performed at the set 16 sysclock cycles. The F280x devices come up as default sysclkout = clkin / 2, so at 20Mhz clkin, each access would take 100ns * 16 = 1.6us.

    2) Yes

    3) See the answer to #1.

     

    Regards,

    Dave Foley

  • 0 in reply to David Foley
    TI__Guru** 111090 points

    Dave,

    Thanks for your reply!

    How slowly the flash access speed! The F280x will maybe reset before the device is initialized to enable the PLL, pipeline mode and configure wait states if there are more static variable to deal, because the watchdog is enable in default. How to avoid this case?

     

    Best Regards,

    Yanming Luo

  • 0 in reply to Yanming Luo
    TI__Guru 61235 points

    Yanming,

     

    You need to disable the watchdog using assembly code BEFORE calling _c_int00 to setup the C environment.  See SPRA958 for code examples that do this.  File is CodeStartBranch.asm.

    Regards,

    David