Hi,
I am using SPI communication on TMS320F28069 (90 MHz) and I think my SPI speed is not at its maximum but I don't know from where it comes from. I transmit 32 bits in 48.9 µs which corresponds to 654 kbps. I think I can go faster, isn't it ? So I give ou the SPI settings part of my soft (I precise that the SPI communication is between two TMS320F28069) and I am in Debug Mode :
/*************************************************************************
* FONCTION : InitSysCtrl
* DESCRIPTION : Initialise le µC
*
*************************************************************************/
void InitSysCtrl(void){
//---------------------------------------------------------------------------
// InitSysCtrl:
//---------------------------------------------------------------------------
// This function initializes the System Control registers to a known state.
// - Disables the watchdog
// - Set the PLLCR for proper SYSCLKOUT frequency
// - Set the pre-scaler for the high and low frequency peripheral clocks
// - Enable the clocks to the peripherals
// Disable the watchdog
DisableDog();
// *IMPORTANT*
// The Device_cal function, which copies the ADC & oscillator calibration values
// from TI reserved OTP into the appropriate trim registers, occurs automatically
// in the Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC and oscillators to function according
// to specification. The clocks to the ADC MUST be enabled before calling this
// function.
// See the device data manual and/or the ADC Reference
// Manual for more information.
/*EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // Enable ADC peripheral clock
(*Device_cal)();
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 0; // Return ADC clock to original state
EDIS;*/
// Select Internal Oscillator 1 as Clock Source (default), and turn off all unused clocks to
// conserve power.
IntOsc1Sel();
// Initialize the PLL control: PLLCR and CLKINDIV
// DSP28_PLLCR and DSP28_CLKINDIV are defined in F2806x_Examples.h
InitPll(DSP28_PLLCR,DSP28_DIVSEL);
// Initialize the peripheral clocks
InitPeripheralClocks();
}
/*************************************************************************
* FONCTION : Init_Pll
* DESCRIPTION : Initialise la Pll
*
*************************************************************************/
void InitPll(Uint16 val, Uint16 divsel){
//---------------------------------------------------------------------------
// Example: InitPll:
//---------------------------------------------------------------------------
// This function initializes the PLLCR register.
volatile Uint16 iVol;
// Make sure the PLL is not running in limp mode
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0){
EALLOW;
// OSCCLKSRC1 failure detected. PLL running in limp mode.
// Re-enable missing clock logic.
SysCtrlRegs.PLLSTS.bit.MCLKCLR = 1;
EDIS;
// Replace this line with a call to an appropriate
// SystemShutdown(); function.
__asm(" ESTOP0"); // Uncomment for debugging purposes
}
// DIVSEL MUST be 0 before PLLCR can be changed from
// 0x0000. It is set to 0 by an external reset XRSn
// This puts us in 1/4
if(SysCtrlRegs.PLLSTS.bit.DIVSEL != 0){
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
EDIS;
}
// Change the PLLCR
if (SysCtrlRegs.PLLCR.bit.DIV != val){
EALLOW;
// Before setting PLLCR turn off missing clock detect logic
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
SysCtrlRegs.PLLCR.bit.DIV = val;
EDIS;
// Optional: Wait for PLL to lock.
// During this time the CPU will switch to OSCCLK/2 until
// the PLL is stable. Once the PLL is stable the CPU will
// switch to the new PLL value.
//
// This time-to-lock is monitored by a PLL lock counter.
//
// Code is not required to sit and wait for the PLL to lock.
// However, if the code does anything that is timing critical,
// and requires the correct clock be locked, then it is best to
// wait until this switching has completed.
// Wait for the PLL lock bit to be set.
// The watchdog should be disabled before this loop, or fed within
// the loop via ServiceDog().
// Uncomment to disable the watchdog
DisableDog();
while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1){
// Uncomment to service the watchdog
// ServiceDog();
}
EALLOW;
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
EDIS;
}
// If switching to 1/2
if((divsel == 1)||(divsel == 2)){
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
EDIS;
}
// If switching to 1/1
// * First go to 1/2 and let the power settle
// The time required will depend on the system, this is only an example
// * Then switch to 1/1
if(divsel == 3){
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
DELAY_US(50L);
SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
EDIS;
}
}
/*************************************************************************
* FONCTION : InitPeripheralClocks
* DESCRIPTION : Initialise les horloges
*
*************************************************************************/
void InitPeripheralClocks(void){
//--------------------------------------------------------------------------
// Example: InitPeripheralClocks:
//---------------------------------------------------------------------------
// This function initializes the clocks to the peripheral modules.
// First the high and low clock prescalers are set
// Second the clocks are enabled to each peripheral.
// To reduce power, leave clocks to unused peripherals disabled
//
// Note: If a peripherals clock is not enabled then you cannot
// read or write to the registers for that peripheral
EALLOW;
// LOSPCP prescale register settings, normally it will be set to default values
// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // GPIO18 = XCLKOUT
SysCtrlRegs.LOSPCP.all = 0x0001;
// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT
//SysCtrlRegs.XCLK.bit.XCLKOUTDIV=2;
// Peripheral clock enables set for the selected peripherals.
// If you are not using a peripheral leave the clock off
// to save on power.
//
// Note: not all peripherals are available on all F2806x derivates.
// Refer to the datasheet for your particular device.
//
// This function is not written to be an example of efficient code.
/*SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
SysCtrlRegs.PCLKCR1.bit.EPWM7ENCLK = 1; // ePWM7
SysCtrlRegs.PCLKCR1.bit.EPWM8ENCLK = 1; // ePWM8
SysCtrlRegs.PCLKCR0.bit.HRPWMENCLK = 1; // HRPWM
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1
SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2
SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1
SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2
SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3
SysCtrlRegs.PCLKCR2.bit.HRCAP1ENCLK = 1; // HRCAP1
SysCtrlRegs.PCLKCR2.bit.HRCAP2ENCLK = 1; // HRCAP2
SysCtrlRegs.PCLKCR2.bit.HRCAP3ENCLK = 1; // HRCAP3
SysCtrlRegs.PCLKCR2.bit.HRCAP4ENCLK = 1; // HRCAP4
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
SysCtrlRegs.PCLKCR3.bit.COMP1ENCLK = 1; // COMP1
SysCtrlRegs.PCLKCR3.bit.COMP2ENCLK = 1; // COMP2
SysCtrlRegs.PCLKCR3.bit.COMP3ENCLK = 1; // COMP3*/
SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
/*SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2
SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA
SysCtrlRegs.PCLKCR3.bit.CLA1ENCLK = 1; // CLA1
SysCtrlRegs.PCLKCR3.bit.USB0ENCLK = 1; // USB0
SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C-A*/
SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A
SysCtrlRegs.PCLKCR0.bit.SPIBENCLK = 1; // SPI-B
/*SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A
SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B
SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A
SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM*/
//SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock
EDIS;
}
void InitSpi(void){
EALLOW;
// Initialize SPI registers
SpibRegs.SPICCR.all = 0x008F; // Reset on
SpibRegs.SPICTL.all = 0x000E; // Enable master mode, normal phase, enable talk, and SPI int disabled.
SpibRegs.SPIBRR = 0x0001;
SpibRegs.SPIPRI.bit.FREE = 1; // Set so breakpoints don't disturb xmission
EDIS;
}
What can be the issue ? Thank you in advance if you have any idea