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Baudrate for High speed UART for F28M35x Concerto Microcontrollers

Hello,

What is the maximum baudrate High speed UART support for F28M35x Concerto Microcontroller?

Please guide me to some reference documentation which I can refer for this calculation.

Regards,
Ankit Gupta

  • Hi Ankit,

    Ankit Gupta1 said:
    What is the maximum baudrate High speed UART support for F28M35x Concerto Microcontroller?

    The Technical Reference Manual suggests for 38400 as maximum in their table.

    Ankit Gupta1 said:
    Please guide me to some reference documentation which I can refer for this calculation.

    Also, I would like you to refer this link which is on similar lines:

    http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/280552.aspx

    Regards,

    Gautam

  • Hey Gautam,

    Thanks a lot for your reply. It helped to understand a bit.

    As mentioned in the link, I also need to use UART at around 5mbps. I will find the config required for it.
    In user manual sec 15 talk about SCI and sec 23 talk about UART. Both shall be same as SCI is also UART.

    Regards,

    Ankit Gupta

  • Ankit Gupta1 said:
    As mentioned in the link, I also need to use UART at around 5mbps. I will find the config required for it.
    In user manual sec 15 talk about SCI and sec 23 talk about UART. Both shall be same as SCI is also UART.

    Good question, actually both indicate the same peripheral; so don't get confused due to their terminologies.

    Regards,

    Gautam

  • Ankit, Gautam,

    Please understand that UART (Master subsystem) and SCI (Control Subsystem) are not the same peripheral. Yes, they both are capable of supporting the usual UART protocols, but the physical designs are completely different. There are different control registers as well as different logic inside of the module. This means that they are not code compatible. 

    Now, For the c28x SCI, The maximum baud rate is 9.375Mbps (LSPCLK/16). This is with LSPCLK = 150MHz (which is the maximum on F28M35x. See Table 5-11 of the F28M35x Datasheet (SPRS742) for this information. The calculation for the baud rate of the c28x SCI is in the register description for the SCI Baud Select registers, Section 15.3.4 of the F28M35x TRM.

    For the M3 UART, the maximum Baud is 12.5Mbps. This is only possible when the M3SSCLK = 100MHz. This calculation is based off of the equations found in 23.3.2 of the TRM. If M3SSCLK is 100MHz and HSE of UARTCTL is set, your minimum divider is 1.0 (BRDI+BRDF). So 100MHz/8 = 12.5Mbps.

    Please keep in mind the ratio between the Master Subsystem Clock (M3SSCLK) and Control subsystem clock (C28SYSCLK) when planning your application. If you choose to use the maximum 12.5Mbps of the M3 UART, your C28SYSCLK will be limited to 100MHz as well.

    I hope this helps. Please do not hesitate to ask any more questions!

    Mark

  • Mark Labbato said:
    I hope this helps. Please do not hesitate to ask any more questions!

    Thanks a lot Mark for the brief explanation! I always thought TI calls its UART peripheral as SCI... Anyways thanks for the clarification.

    Regards,

    Gautam

  • Thanks for your detailed clarification Mark,

    Couple of doubts I have.

    1. M3 (Master subsystem) - supports 5 UART, all 5 can work independently at 12.5Mbps?

    2. Why C28SYSCLK will be limited to 100MHz? Are both working on single clock?

    Regards,

    Ankit Gupta

  • Ankit,

    1. Yes, there should be no problems operating all at the maximum speed. I do caution that even though the UART is capable of reaching these speeds, other devices may not. It is very fast for the standard UART protocols. You will need to pick your baud rate such that it is compatible with the other devices. 

    2. Please refer to Figure 2-11 of the Datasheet. Both subsystems are operating off of the same PLL. The Maximum PLLSYSCLK is 150MHz. The M3SSCLK (Master subsystem in the diagram) can be either PLLSYCLK /1, /2, or /4 with a restriction that it must not exceed 100MHz. Let us look at a few combinations of Subsystem clock speeds, all of which are valid:

    PLLSYCLK C28SYSCLK M3SSCLK
    150 150 75
    150 150 37.5
    100 100 100
    100 100 50
    100 100 25
    75 75 75
    75 75 37.5
    75 75 18.75
    60 60 60

    Based on the PLL divider settings, you are limited to a specific combination of Subsystem clocks based on your PLLSYSCLK selection as you can see in the table and Figure 2-11

    To bring this back to the original question, if you wish to have UART at 12.5Mbps, consider what is running on your Control subsystem and ask which is more important to your application. If the throughput of 12.5Mbps x 5 UARTs is more important than running at your control subsystem as fast as possible, then that is what you must do..

    Thanks,

    Mark