I2C slave R/W# bit state?

TobyM

Hi Folks,

I am using a F2802x as an I2C slave. How can I know the state of the R/W# bit in the received address byte from a master? Does the I2CSTR.SDIR bit reflect this? Or maybe I2CMDR.TRX?

Thanks :)

ALSO: when a slave, does it matter what the module clock is set to with the IPSC? or is this used only for the clock output when a master?

over 9 years ago

0 Adam Haun over 9 years ago

TI__Expert 8950 points

The SDIR bit should tell you the direction after the slave has been addressed.

The module clock must be between 7 MHz and 12 MHz in both master and slave mode.

0 TobyM over 9 years ago in reply to Adam Haun

Genius 5200 points

Hi Adam,

Thanks for your info.

On the issue of the module clock, what I meant was is it required for the slave and master module clocks to match?

My issue is if the system master is not a device that the module clock frequency is known for, how should the slave module clock be set?

Thanks

0 Adam Haun over 9 years ago in reply to TobyM

TI__Expert 8950 points

The module clock is just a timing reference. Keeping it in the 7 - 12 MHz range ensures that the module will use the correct setup and hold times for signals transitions. It doesn't have to match the master. Since the master generates the SCL clock, there's no other timing setup needed for the slave.

0 Truong Nguyen Xuan66 over 8 years ago in reply to Adam Haun

Prodigy 40 points

Hi Adam Haun,

I'm using F28069 as I2C master without fifo...

I would like to be helped:

How can I indicate the fist byte(addressing) with read or write with slave?

0 user1745435 over 8 years ago in reply to Adam Haun

Prodigy 190 points

hi,Adam;

The SDIR bit is set after SDA receive the 7 bits address?when master read from slaver ,the first address+w can affect the SDIR bit?the second address+R decide the SDIR bit ? wait for your reply~~

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I2C slave R/W# bit state?