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FaultIsr() on Master M3 of F28M35

Hello,

Unfortunately, when my program is running FaultIsr() interrupt is triggered.

1 - Where can I find information(documentation) to get the cause of this ISR ?

2 -I use uart. I noticed that this interruption is triggered from the moment the uart receives data.

   Here is the sample code of the Uart

//Initialization

#ifdef UART0


// Configure the GPIO settings for the UART0 pins. This function also gives
// control of these pins to the UART0 hardware. Consult the data sheet to
// see which functions are allocated per pin.
// The pins are assigned as follows:
GPIOPinTypeUART(GPIO_PORTJ_BASE, GPIO_PIN_3); 
GPIOPinTypeUART(GPIO_PORTJ_BASE, GPIO_PIN_2); 

// Configure the pin muxing for UART0 functions 
GPIOPinConfigure(GPIO_PJ3_U0RX); 
GPIOPinConfigure(GPIO_PJ2_U0TX); 

//PULL UP
GPIOPadConfigSet(GPIO_PORTJ_BASE,GPIO_PIN_3,GPIO_PIN_TYPE_STD_WPU);//push pull with weak pull up 
GPIOPadConfigSet(GPIO_PORTJ_BASE,GPIO_PIN_2,GPIO_PIN_TYPE_STD_WPU);//push pull with weak pull up 

// 8 bits, 1 bit de stop, pas de bit de parité, en 9600 bauds
UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(SYSTEM_CLOCK_SPEED), 9600, //(JPP)
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE));

// Enable the UART interrupt.
IntRegister(INT_UART0, UARTIntHandler); 
IntEnable(INT_UART0); 
UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT/*| UART_INT_TX */); 

#endif

(...)

//Interrupt

void UARTIntHandler(void) 
{

(...)

unsigned long ulStatus;
// Get the interrrupt status.
ulStatus = UARTIntStatus(UART0_BASE, true);
// Clear the asserted interrupts.
UARTIntClear(UART0_BASE, ulStatus);

(...)

}

Regards

  • Hi Joel,

    Cortex M3 has different types of Faults. Hard Fault/Bus Fault/Usage Fault and for each of these, there are status registers inside M3. Please refer Cortex-M3 TRM to find the details of these status registers.

    If you are getting this fault when UART interrupt is getting triggered then, please check the mapping of interrupt vector table. We have ECC errors (uncorrectable, 2-bot or more) also which could generate the BusFault so check that as well. This can be check by looking at error status registers of Flash and RAM. Please refer the TRM sections  "5.3.10" for Flash and "5.1.1.6"/"5.1.1.7" for RAM.

    Regards,

    Vivek Singh