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F28377S HRPWM PSFB configuration

Other Parts Discussed in Thread: CONTROLSUITE

Hi,

I am trying to make PSFB configuration with F28377S. Is it possible to make high resolution period and high resolution phase control at the same time with fixed dead time with F28377S?

Refering TRM chapter 14.1

• Enables high resolution output swapping on the EPWMxA and EPWMxB output
• Enables high-resolution output on EPWMxB signal output via inversion of EPWMxA signal output

Does these mean that, EPWMxB is an inversion of EPWMxA for F28377S, and there is no dead band support for EPWMxB? because next line is a bit confusing


• Enables high-resolution period, duty and phase control on the EPWMxA and EPWMxB output on
devices with an ePWM module.

Or this mean that EPWMxB is not just an inversion of EPWMxA, and EPWMxB has dead band support?

Is there any sample code?

What i found from controlsuite is,

C:\ti\controlSUITE\device_support\F2837xS\v170\F2837xS_examples_Cpu1\hrpwm_prdupdown_sfo_v8

for high resolution period control.

Or can i think this as a starting point

C:\ti\controlSUITE\libs\app_libs\digital_power\f28x7x_v1.0\CNF\PWM_1chHiRes_Cnf.c

is there any where else that i should check?

Thank you for your help

 

  • Hi,

    This is possible.

    The HRPWM output on EPWMxB can be an independent output than the xA output. There are a couple of different ways to do this.

    1. Use CMPA:CMPAHR for the xA output and use RED and FED in the deadband module to generate an inverted xB output using active high complementary (AHC) configuration (this is different than the inversion you've mentioned). You will need to write to the CMPB:CMPBHR register to obtain high resolution output on xB output.

    2. Independently generate xA and xB outputs using AQCTLA and AQCTLB. AQCTLB should be configured to generate inverted PWM signals than the actual ones desired on the xB output. The correct xB signal is obtained in the dead-band module by inversion (DBCTL[POLSEL] bits). RED and FED in the dead-band module provide required dead-band. CMPA:CMPAHR and CMPB:CMPBHR should be written to (similar to case 1).

    Note that the DBCTL[IN_MODE] bits should be correctly configured in (1) and (2).

    I would recommend using the 2nd method above. You can use the hrpwm_prdupdown_sfo_v8 example as the starting point.

    I hope this helps.

    Hrishi

  • Hi,

    I will try the second configuration, thank you very much.

  • Hello Hrishi,

    First of all thank you for the valuable information. Based on C:\ti\controlSUITE\device_support\F2837xS\v170\F2837xS_examples_Cpu1\hrpwm_prdupdown_sfo_v8, i made some changes and FSPB configuration with high resolution period and high resolution phase control is working based on oscilloscope readings.

    1) I attached configuration code, before i implement on physical system, could you please have a look and share your opinion 

    2) e2e.ti.com/support/microcontrollers/c2000/f/171/p/438960/1579295#1579295   as you mentioned on this post,

    for ePWM[n], i set   (*ePWM[n]).TBPRD = period-1;

    and for ePWM[n+1], i set   (*ePWM[n+1]).TBPRD = period-2; 

    3) e2e.ti.com/support/microcontrollers/c2000/f/171/p/389087/1377140 and as you mentioned in this post,

    for ePWM[n+1], i set,     (*ePWM[n+1]).TBCTL2.bit.PRDLDSYNC = 2;           // Shadow to Active Load of TBPRD occurs only when a SYNC is received

    PSFB HRPWM.txt
     //---------------------------------------------
       // ePWM(n) init.  Note EPWM(n) is the Master
        (*ePWM[n]).TBCTL.bit.PRDLD = TB_SHADOW;            // set Shadow load
        (*ePWM[n]).TBPRD = period-1;                       // 
        (*ePWM[n]).CMPA.bit.CMPA = period / 2;             // set duty 50% initially
        (*ePWM[n]).CMPA.bit.CMPAHR = (1 << 8);             // initialize HRPWM extension
        (*ePWM[n]).CMPB.bit.CMPB = period / 2;             // set duty 50% initially
        (*ePWM[n]).CMPB.all |= 1;
        (*ePWM[n]).TBPHS.all = 0;
        (*ePWM[n]).TBCTR = 0;
    
        (*ePWM[n]).TBCTL.bit.CTRMODE = TB_COUNT_UP;        // Select up count mode
        (*ePWM[n]).TBCTL.bit.PHSEN = TB_DISABLE;
        (*ePWM[n]).TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; 	   //used to sync EPWM(n+1) "down-stream"
    
        (*ePWM[n]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
        (*ePWM[n]).TBCTL.bit.CLKDIV = TB_DIV1;              // TBCLK = SYSCLKOUT
        (*ePWM[n]).TBCTL.bit.FREE_SOFT = 11;
    
        (*ePWM[n]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;      // LOAD CMPA on CTR = 0
        (*ePWM[n]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
        (*ePWM[n]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
        (*ePWM[n]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    
    
        (*ePWM[n]).AQCTLA.bit.ZRO = AQ_SET;               // PWM toggle high/low
        (*ePWM[n]).AQCTLA.bit.CAU = AQ_CLEAR;
        (*ePWM[n]).AQCTLB.bit.ZRO = AQ_SET;
        (*ePWM[n]).AQCTLB.bit.CBU = AQ_CLEAR;
    
        // DeadBand Control Register
        (*ePWM[n]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
        (*ePWM[n]).DBCTL.bit.POLSEL = DB_ACTV_HIC; 			// Active Hi Complimentary
        (*ePWM[n]).DBRED = ((period/25) + 5);
        (*ePWM[n]).DBFED = ((period/25) + 5);
    
        EALLOW;
        (*ePWM[n]).HRCNFG.all = 0x0;
        (*ePWM[n]).HRCNFG.bit.EDGMODE = HR_BEP;          // MEP control on both edges
        (*ePWM[n]).HRCNFG.bit.CTLMODE = HR_CMP;          // CMPAHR and TBPRDHR HR control
        (*ePWM[n]).HRCNFG.bit.HRLOAD  = HR_CTR_ZERO;	 // load on CTR = 0
        (*ePWM[n]).HRCNFG.bit.EDGMODEB = HR_BEP;         // MEP control on both edges
        (*ePWM[n]).HRCNFG.bit.CTLMODEB = HR_CMP;         // CMPBHR and TBPRDHR HR control
        (*ePWM[n]).HRCNFG.bit.HRLOADB  = HR_CTR_ZERO;	 // load on CTR = 0
        (*ePWM[n]).HRCNFG.bit.AUTOCONV = 1;              // Enable autoconversion for HR period
    
        (*ePWM[n]).HRPCTL.bit.TBPHSHRLOADE = 1;          // Enable TBPHSHR sync (required for updwn count HR control)
        (*ePWM[n]).HRPCTL.bit.HRPE = 1;                  // Turn on high-resolution period control.
    
        EDIS;
        //---------------------------------------------
        // ePWM(n+1) init.  EPWM(n+1) is a slave
        (*ePWM[n+1]).TBCTL.bit.PRDLD = TB_SHADOW;          	 // set Shadow load
        (*ePWM[n+1]).TBCTL2.bit.PRDLDSYNC = 2;          	 // Shadow to Active Load of TBPRD occurs only when a SYNC is received
        (*ePWM[n+1]).TBPRD = period-2;                       // PWM frequency = 1 / period
        (*ePWM[n+1]).CMPA.bit.CMPA = period / 2;             // set duty 50% initially
        (*ePWM[n+1]).CMPA.bit.CMPAHR = (1 << 8);             // initialize HRPWM extension
        (*ePWM[n+1]).CMPB.bit.CMPB = period / 2;             // set duty 50% initially
        (*ePWM[n+1]).CMPB.all |= 1;
        (*ePWM[n+1]).TBPHS.all = 0;
        (*ePWM[n+1]).TBCTR = 0;
    
        (*ePWM[n+1]).TBCTL.bit.CTRMODE = TB_COUNT_UP;     // Select up-down count mode
    	(*ePWM[n+1]).TBCTL.bit.PHSEN = TB_ENABLE;
        (*ePWM[n+1]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; 		 // Sync "flow through" mode
    
        (*ePWM[n+1]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
        (*ePWM[n+1]).TBCTL.bit.CLKDIV = TB_DIV1;              // TBCLK = SYSCLKOUT
        (*ePWM[n+1]).TBCTL.bit.FREE_SOFT = 11;
    
        (*ePWM[n+1]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;      // LOAD CMPA on CTR = 0
        (*ePWM[n+1]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
        (*ePWM[n+1]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
        (*ePWM[n+1]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    
    
        (*ePWM[n+1]).AQCTLA.bit.ZRO = AQ_SET;               // PWM toggle high/low
        (*ePWM[n+1]).AQCTLA.bit.CAU = AQ_CLEAR;
        (*ePWM[n+1]).AQCTLB.bit.ZRO = AQ_SET;
        (*ePWM[n+1]).AQCTLB.bit.CBU = AQ_CLEAR;
    
        // DeadBand Control Register
        (*ePWM[n+1]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
        (*ePWM[n+1]).DBCTL.bit.POLSEL = DB_ACTV_HIC;		 // Active Hi Complimentary
        (*ePWM[n+1]).DBRED = ((period/25) + 5);
        (*ePWM[n+1]).DBFED = ((period/25) + 5);
    
        EALLOW;
        (*ePWM[n+1]).HRCNFG.all = 0x0;
        (*ePWM[n+1]).HRCNFG.bit.EDGMODE = HR_BEP;          // MEP control on both edges
        (*ePWM[n+1]).HRCNFG.bit.CTLMODE = HR_CMP;          // CMPAHR and TBPRDHR HR control
        (*ePWM[n+1]).HRCNFG.bit.HRLOAD  = HR_CTR_ZERO;	   // load on CTR = 0
        (*ePWM[n+1]).HRCNFG.bit.EDGMODEB = HR_BEP;         // MEP control on both edges
        (*ePWM[n+1]).HRCNFG.bit.CTLMODEB = HR_CMP;         // CMPBHR and TBPRDHR HR control
        (*ePWM[n+1]).HRCNFG.bit.HRLOADB  = HR_CTR_ZERO;    // load on CTR = 0
        (*ePWM[n+1]).HRCNFG.bit.AUTOCONV = 1;              // Enable autoconversion for HR period
    
        (*ePWM[n+1]).HRPCTL.bit.TBPHSHRLOADE = 1;          // Enable TBPHSHR sync (required for updwn count HR control)
        (*ePWM[n+1]).HRPCTL.bit.HRPE = 1;                  // Turn on high-resolution period control.
    
        EDIS;
    
        //---------------------------------------------
    

  • Hi,

    I am sorry for the delay. I was out of office for the last few weeks. Did this configuration work for you? Let me know if you have any other questions.

    Hrishi

  • Hi,

    İ did not try on physical system, but oscilloscope readings seem ok. Thank you very much