shared register with atomic operations F28377D

Hi Rony,

There are atomic instructions in the C28x ISA (e.g. test and set) that can be used to build synchronization mechanisms to control access to shared resources within the context of a single CPU. (see spru430f)

If you need to control access to shared resources, I think you will need to designate one CPU as keeper of the synchronization primitives. If the other CPU needs to lock access to a shared resource, it needs to send an IPC to the master CPU, which can then initiate an interrupt on the master CPU, which can try to lock the primitive. Even if the IPC interrupt occurs in the middle of the master CPU trying to lock the primitive from some other part of its code, since the instructions are atomic in the context of the master CPU there shouldn't be inconsistent results when trying to acquire the primitive.

Hi Devin,

I understand your point but i'm not sure, it's completely satisfy my need.

I'm dealing with a safety critical real-time application, let say i have a task T2 in cpu2 which send an IPC to task T1 in cpu1, the task T1 may be execute a critical code section, (cannot be interrupt to service the IPC immediately) and moreover the critical code section have nothing to do with the shared resource, From my understanding, with the proposed solution, task T2 need to wait the execution of the critical code section on cpu1 plus the treatment of the IPC to know if the shared resource is available, is that correct?

A solution will be to move T2 on cpu1, but i really need to use the capacity of cpu2, and T1 and T2 are tasks with hard deadlines.

A test set atomic operation in a register shared by both cpu, could be helpfull is such situation

Thanks,
regards,
Rony.

Hi Rony,

It'll be good if you could give example of shared resource or register in this case? Most of the shared resources are allocated to CPU1 or CPU2 as part of system initialization hence need not to have IPC handshake during application run time. Some registers are semaphore based and there an IPC handshake may be needed but most of these are related to clock configuration which are also done as part of system initialization. So it really depends on which shared resource/register we are discussing here and what is the use case.

Regards,

Vivek Singh

Hi Vivek,

The shared resource in my application is a part of the global shared RAM of F28377D.
The use case is: a task T1 on cpu1 is writing and reading that part of memory, the task T2 on cpu2 is reading the same part of memory.

I want to add a software synchronization mechanism ( let's say a lock, without adding too much latency) to be sure that when task T2 on cpu2 read the shared zone, task T1 on cpu1 is not writing something at the same time.

That software synchronization mechanism need a hardware instruction on a register/memory (atomic test set, for example) which guarantee that the test and the set of the register/memory is atomic, even if the operation is realized simultaneously on both cpu.

I believe the response of Richard was correct, the feature does not exist on F28377D.

Thanks,
Regards,
Rony