Hello,
I am running a motor control algorithm that needs to be synchronized to the PWM modules but every 3rd PWM cycle is too fast for my algorithm. What I want to do is run a counter in the PWM ISR and trigger one of the reserved PIE interrupts every 4th PMW interrupt. The reserved ISR will sample the ADC registers then trigger an SOC so that I can run my control algorithm and the ADC sampling in parallel. The PWM interrupt will have higher priority so that it will restart the counter, and then update the ePWM comparison registers and fire the next reserved ISR with the correct timing.
What I know:
How to assign priorities in software to nest my interrupts.
How to trigger the ADC SOC from software.
What I cannot figure out:
How to trigger one of the reserved interrupts in PIE group 11 or 12.
Reference:
On page 123 of "TMS32x2833x, 2823x System Control and Interrupts" it says:
"Out of the 96 possible MUXed interrupts in Table 111, 43 interrupts are currently used. The remaining
interrupts are reserved for future devices. These reserved interrupts can be used as software interrupts if
they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a
peripheral. Otherwise, interrupts coming from peripherals may be lost by accidentally clearing their flags
when modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts can be used as software interrupts:
1. No peripheral within the group is asserting interrupts.
2. No peripheral interrupts are assigned to the group. For example, PIE group 11 and 12 do not have any
peripherals attached to them."
However, there is no mention of how this could be implemented, and the PIEIFRx registers can only be cleared, not written to. Does anyone know how to do this?
Thank you.
