Can't initialize external memory interface on TMS320F2812

Jens Biltoft

Other Parts Discussed in Thread: CODECOMPOSER, SYSBIOS

I have been working for a while on a task to migrate our old code from codecomposer 3.1 to codecomposer 6.

This has been a bit of a challange, but now I have managed to create a SYSBIOS cfg file, compile the code, link the output, load it to a JTAG debugger and get the code to run to main - so far so good.

One of the first functions is main is to initialize the external memory interface, but unfortunately this fails, and the code hangs forever in a while loop waiting for WLEVEL bit to become 0.

/**********************************************************************
* Function: main()
*
* Description: Main function.
**********************************************************************/
void main(void)
{
  int i;
  uint16 x = 0;

  /*** Initialization ***/
  // Initialize the CPU (FILE: DSP281x_SysCtrl.c)
  InitSysCtrl();                         
  // Initialize the external memory interface (FILE: Xintf.c)
  InitXintf();

/**********************************************************************
* Function: InitXintf()
*
* Description: Initializes the external memory interface on the F2812.
**********************************************************************/
void InitXintf(void)
{

/*** XINTCNF2 Register ***/
	XintfRegs.XINTCNF2.bit.XTIMCLK = 1;			// XTIMCLK=SYSCLKOUT/2
	XintfRegs.XINTCNF2.bit.CLKOFF = 0;			// XCLKOUT is enabled
	XintfRegs.XINTCNF2.bit.CLKMODE = 0;			// XCLKOUT = XTIMCLK

// Make sure write buffer is empty before configuring buffering depth
	while(XintfRegs.XINTCNF2.bit.WLEVEL != 0);	// poll the WLEVEL bit
	XintfRegs.XINTCNF2.bit.WRBUFF = 0;			// No write buffering

So the question is if the external memoryinteface has to be initialized in a different way under SYSBIOS that it should under the old DSPBIOS?

I have attached the CCS6 project that I am using

more info on my setup

Custom HW platform (do not know if it is based on an eval board, but most likely it is)

bios_6_46_00_23

\compiler\ti-cgt-c2000_15.12.1.LTS

CCS6_project.zip

This thread is is continuation of this thread

Thanks

Jens

over 8 years ago

0 Richard Poley over 8 years ago

TI__Mastermind 27200 points

Jens,

From your CCSv6 linker command file I can see you are mapping the .text section into zone 6. This is a region of external memory accessed over the XINTF. You are effectively configuring the XINTF while running code through it. I think this is why you're having the problem. In your CCSv3 cmd file, the .text section was in HOSARAM (i.e. internal RAM).

Typically a user will load the XINTF configuration code into internal RAM and run it from there. For an example of how to do this, try running the "run_from_xintf" example in the header file package for this device:
http://www.ti.com/tool/sprc097

Regards,

Richard

0 Jens Biltoft over 8 years ago in reply to Richard Poley

Expert 1220 points

Hi Richard

I see the problem in running code from XINTF while configuring the XINTF.

If I move the .text to H0SARAM it will not fit in the memory. It seems that the size of .text have increased dramatically in CCSv6 compared to CCSv3?

If I look in my old .map file I can see that the length of .text is 0x1ae8

section   page    origin      length       input sections
--------  ----  ----------  ----------   ----------------
.text      0    003f8000    00001ae8

If I compare this to the map file from my empty project, I can see that the length of .text has increased to

section   page    origin      length       input sections
--------  ----  ----------  ----------   ----------------
.text      0    003ec000    00002d9f

If I compile my original code with CCsv6 the size of .text is 0x3c22 !!!

Therefore It is no longer possible to place .text in H0SARAM, so I looked in the examples you referenced to, and saw that .text should or could be placed in FLASHA together with .cinit and .pinit. But when I tried that it was still too big so I modified my .cmd file to

SECTIONS
{
 
   /* Allocate program areas: */
   .cinit              : > FLASHC      PAGE = 0
   .pinit              : > FLASHA,     PAGE = 0
   .text               : > FLASHD      PAGE = 0

whiched made it possible to link my project.

But when I try to load the out file to the Debugger I get this error

C28xx: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map.

C28xx: File Loader: Verification failed: Values at address 0x3EC000@Program do not match Please verify target memory and memory map.

C28xx: GEL: File: C:\Users\jepbi\VPC_2_CC6\GI_Driver_empty\Debug\GI_Driver_empty.out: a data verification error occurred, file load failed.

I have attached the modified .cmd file, can you please take a look at it and see what I am doing wrong?

F2812_cmd.txt

/*
// TI File $Revision: /main/2 $
// Checkin $Date: April 28, 2005   15:19:56 $
//###########################################################################
//
// FILE:	F2812.cmd
//
// TITLE:	Linker Command File For F2812 Device
//
//###########################################################################
// $TI Release: $
// $Release Date: $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file, 
// add the header linker command file directly to the project. 
// The header linker command file is required to link the
// peripheral structures to the proper locations within 
// the memory map.
//
// The header linker files are found in <base>\DSP281x_Headers\cmd
//   
// For BIOS applications add:      DSP281x_Headers_nonBIOS.cmd
// For nonBIOS applications add:   DSP281x_Headers_nonBIOS.cmd    
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the 
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper 
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP281x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l DSP281x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\DSP281x_headers\cmd to the
   library search path under project->build options, linker tab, 
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F2812  
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes: 
         Memory blocks on F2812 are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.  
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program 
         and/or data. 
*/

MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

   ZONE0       : origin = 0x002000, length = 0x002000     /* XINTF zone 0 */
   ZONE1       : origin = 0x004000, length = 0x002000     /* XINTF zone 1 */
   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   ZONE2       : origin = 0x080000, length = 0x080000     /* XINTF zone 2 */
   /* original value ZONE6       : origin = 0x100100, length = 0x080000 */    /* XINTF zone 6 */
   ZONE6       : origin = 0x100100, length = 0x07ff00     /* XINTF zone 6 */
   OTP         : origin = 0x3D7800, length = 0x000800     /* on-chip OTP */
   FLASHJ      : origin = 0x3D8000, length = 0x002000     /* on-chip FLASH */
   FLASHI      : origin = 0x3DA000, length = 0x002000     /* on-chip FLASH */
   FLASHH      : origin = 0x3DC000, length = 0x004000     /* on-chip FLASH */
   FLASHG      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
   FLASHF      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */
   FLASHE      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
   FLASHD      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
   FLASHC      : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH */
   FLASHA      : origin = 0x3F6000, length = 0x001F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL     : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

/* ZONE7       : origin = 0x3FC000, length = 0x003FC0     /* XINTF zone 7 available if MP/MCn=1 */ 
   ROM         : origin = 0x3FF000, length = 0x000FC0     /* Boot ROM available if MP/MCn=0 */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM (MP/MCn=0) or XINTF zone 7 (MP/MCn=1) */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM (MP/MCn=0) or XINTF zone 7 (MP/MCn=1) */

/* user modifications  start */

   BOOTMEM     : origin = 0x100000, length = 0x000100

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   RAMM0       : origin = 0x000000, length = 0x000400     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   FLASHB      : origin = 0x3F4000, length = 0x002000     /* on-chip FLASH */
   RAMH0       : origin = 0x3F8000, length = 0x002000     /* on-chip RAM block H0 */

/* user modifications  start */
   PIEVECT     : origin = 0x000d00, length = 0x000100     /**/
   FPGA_MEM    : origin = 0x002000, length = 0x0000ff     /**/

/* from DSP281x_Headers_BIOS.cmd */
   DEV_EMU     : origin = 0x000880, length = 0x000180     /* device emulation registers */
   FLASH_REGS  : origin = 0x000A80, length = 0x000060     /* FLASH registers */
   CSM         : origin = 0x000AE0, length = 0x000010     /* code security module registers */
   XINTF       : origin = 0x000B20, length = 0x000020     /* external interface registers */
   CPU_TIMER0  : origin = 0x000C00, length = 0x000008     /* CPU Timer0 registers (CPU Timer1 and Timer2 are reserved for BIOS)*/
   PIE_CTRL    : origin = 0x000CE0, length = 0x000020     /* PIE control registers */
   ECANA       : origin = 0x006000, length = 0x000040     /* eCAN control and status registers */
   ECANA_LAM   : origin = 0x006040, length = 0x000040     /* eCAN local acceptance masks */
   ECANA_MOTS  : origin = 0x006080, length = 0x000040     /* eCAN message object time stamps */
   ECANA_MOTO  : origin = 0x0060C0, length = 0x000040     /* eCAN object time-out registers */
   ECANA_MBOX  : origin = 0x006100, length = 0x000100     /* eCAN mailboxes */
   SYSTEM      : origin = 0x007010, length = 0x000020     /* System control registers */
   SPIA        : origin = 0x007040, length = 0x000010     /* SPI registers */
   SCIA        : origin = 0x007050, length = 0x000010     /* SCI-A registers */
   XINTRUPT    : origin = 0x007070, length = 0x000010     /* external interrupt registers */
   GPIOMUX     : origin = 0x0070C0, length = 0x000020     /* GPIO mux registers */
   GPIODAT     : origin = 0x0070E0, length = 0x000020     /* GPIO data registers */
   ADC         : origin = 0x007100, length = 0x000020     /* ADC registers */
   EVA         : origin = 0x007400, length = 0x000040     /* Event Manager A registers */
   EVB         : origin = 0x007500, length = 0x000040     /* Event Manager B registers */
   SCIB        : origin = 0x007750, length = 0x000010     /* SCI-B registers */
   MCBSPA      : origin = 0x007800, length = 0x000040     /* McBSP registers */
   CSM_PWL     : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations. */


}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/ 
 
SECTIONS
{
 
   /* Allocate program areas: */
   .cinit              : > FLASHC      PAGE = 0
   .pinit              : > FLASHA,     PAGE = 0
   .text               : > FLASHD      PAGE = 0
   codestart           : > BEGIN       PAGE = 0
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 0

   csmpasswds          : > CSM_PWL     PAGE = 0
   csm_rsvd            : > CSM_RSVD    PAGE = 0
   
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0       PAGE = 1
   .ebss               : > RAML1       PAGE = 1
   .esysmem            : > RAMH0       PAGE = 1

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA      PAGE = 0
   .switch             : > FLASHA      PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHC      PAGE = 0                  /* Math Code */
   IQmathTables        : > ROM         PAGE = 0, TYPE = NOLOAD   /* Math Tables In ROM */

   /* .reset is a standard section used by the compiler.  It contains the */ 
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */ 
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT

/* user modifications  start */
   .cio                : > FLASHA          PAGE = 0
   .boot               : > BOOTMEM         PAGE = 0

    .z6code :
    {
        Adc.obj (.text)
        DAC.obj (.text)
        DSP281x_Ev.obj (.text)
        DSP281x_Spi.obj (.text)
        DSP281x_SysCtrl.obj (.text)
        FIFO_data.obj (.text)
        Gpio.obj (.text)
        Xintf.obj (.text)
    } > ZONE6

/*** The PIE Vector table is called PIEVECT by DSP/BIOS ***/
   PieVectTableFile  : > PIEVECT,     PAGE = 1,  TYPE = DSECT

/*** Peripheral Frame 0 Register Structures ***/
   DevEmuRegsFile    : > DEV_EMU,     PAGE = 1
   FlashRegsFile     : > FLASH_REGS,  PAGE = 1
   CsmRegsFile       : > CSM,         PAGE = 1
   XintfRegsFile     : > XINTF,       PAGE = 1
   CpuTimer0RegsFile : > CPU_TIMER0,  PAGE = 1
   PieCtrlRegsFile   : > PIE_CTRL,    PAGE = 1

/*** Peripheral Frame 1 Register Structures ***/
   SysCtrlRegsFile   : > SYSTEM,      PAGE = 1
   SpiaRegsFile      : > SPIA,        PAGE = 1
   SciaRegsFile      : > SCIA,        PAGE = 1
   XIntruptRegsFile  : > XINTRUPT,    PAGE = 1
   GpioMuxRegsFile   : > GPIOMUX,     PAGE = 1
   GpioDataRegsFile  : > GPIODAT      PAGE = 1
   AdcRegsFile       : > ADC,         PAGE = 1
   EvaRegsFile       : > EVA,         PAGE = 1
   EvbRegsFile       : > EVB,         PAGE = 1
   ScibRegsFile      : > SCIB,        PAGE = 1
   McbspaRegsFile    : > MCBSPA,      PAGE = 1

/*** Peripheral Frame 2 Register Structures ***/
   ECanaRegsFile     : > ECANA,       PAGE = 1
   ECanaLAMRegsFile  : > ECANA_LAM    PAGE = 1
   ECanaMboxesFile   : > ECANA_MBOX   PAGE = 1
   ECanaMOTSRegsFile : > ECANA_MOTS   PAGE = 1
   ECanaMOTORegsFile : > ECANA_MOTO   PAGE = 1

/*** Code Security Module Register Structures ***/
   CsmPwlFile        : > CSM_PWL,     PAGE = 1

/*** Externaly placed data, FPGA ***/
   GIExtMem : > FPGA_MEM PAGE = 1
   RIExtMem : > FPGA_MEM PAGE = 1

}

/Jens

FLASHA

0 Richard Poley over 8 years ago in reply to Jens Biltoft

TI__Mastermind 27200 points

Jens,

I'm not sure why your .out file isn't loading correctly. Do you have communication with the device? When you launch the target configuration in CCS and go to the Debug perspective, are you able to connect to the device?

Regarding the difference in code size, the different tools may account for some of this but it's possible you have different optimizer settings in your new project. Can you take a look at what you had for the older CCSv3 project and ensure they're the same this time?

Regards,

Richard

0 Jens Biltoft over 8 years ago in reply to Richard Poley

Expert 1220 points

Yes I can connect to the device, and load other out files, and even single step though these applications. It is only when I try to load the out file that I have just generated that I see the problem.

In my old project I have these options

-g -q -pr -pdsr552 -pden -ml -mn -v28

and the linker uses these options

- c -w -x

If I compare with the optionst used in the CCSv6 project they are

-g -ml -mt -v28 -ms

--float_support=softlib

-O4 --opt_for_speed=1

--advice:performance=all

--define=LARGE_MODEL

--define=f2812_RAM

--display_error_number

--diag_warning=225

--diag_warning=255

--diag_wrap=off

--gen_func_subsections=on

and the linker uses these options

-g -v28 -ml -mt -ms -z

--float_support=softlib

-O4 --opt_for_speed=1

--advice:performance=all

--define=LARGE_MODEL

--define=f2812_RAM

--display_error_number

--diag_warning=225

--diag_warning=255

--diag_wrap=off

--gen_func_subsections=on

-m"GI_Driver.map"

--warn_sections "

--reread_libs

--diag_wrap=off

--display_error_number

--xml_link_info="GI_Driver_linkInfo.xml"

--rom_model

Best

Jens

Can

't initialize external memory interface on TMS320F2812

0 Ricky Lau over 8 years ago in reply to Jens Biltoft

TI__Genius 11435 points

Jens,

Is it possible for you to share the .out file you are loading?

Based on your post, you are getting the following warning message:

"C28xx: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map."

I want to find out which section of your program is writing to memory that is not writable.

You are also getting the following error message:

"C28xx: File Loader: Verification failed: Values at address 0x3EC000@Program do not match Please verify target memory and memory map."

Can you check what the memory at that address looks like after loading your program? Did any data get loaded to this Flash sector (D)?

Can you also try enabling "Verbose Output" during program load. You can enable it by opening the 'Toosl -> On-chip Flash' menu item, and scrolling to the bottom of the view. This will add additional logs into the console during program load.

Thanks,
Ricky

0 Jens Biltoft over 8 years ago in reply to Ricky Lau

Expert 1220 points

I have attached the .out file and the map file

I cannot find the option you mention there is not menu called On-Chip Flash under Tools

You can see the memory at address 03ec000 together with the Tools menu here

Best

Jens

GI_Driver_empty.out.txt

GI_Driver_empty.map.txt

0 Ricky Lau over 8 years ago in reply to Jens Biltoft

TI__Genius 11435 points

Jens,

Can you send me the ccxml file you are using? And did you create it yourself? I noticed if I configure for a C6713 myself, it doesn't have the C28 cores in it. Based on the fact that you do not see the On-Chip Flash menu entry on (at least) one of your C28 cores, there might be something wrong with the ccxml file you are using that might be preventing you from writing to Flash memory on your C28 cores.

Thanks,
Ricky

0 Jens Biltoft over 8 years ago in reply to Ricky Lau

Expert 1220 points

I have attached the ccxml file.

The board that I am working is a bit complex, it has a C6713 processor as main DSP, and it has two F2812 processors as secondary motor controllers. The 3 processors are connected to the same JTAG interface, and this is why you see three processores in the debug window.

best

Jens

C6713.ccxml.txt

<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
    <configuration XML_version="1.2" id="Spectrum Digital XDS510USB Emulator_0">
        <instance XML_version="1.2" desc="Spectrum Digital XDS510USB Emulator_0" href="connections/SD510USB_Connection.xml" id="Spectrum Digital XDS510USB Emulator_0" xml="SD510USB_Connection.xml" xmlpath="connections"/>
        <connection XML_version="1.2" id="Spectrum Digital XDS510USB Emulator_0">
            <instance XML_version="1.2" href="drivers/sdgo6xusb.xml" id="drivers" xml="sdgo6xusb.xml" xmlpath="drivers"/>
            <instance XML_version="1.2" href="drivers/sdgo28xusb.xml" id="drivers" xml="sdgo28xusb.xml" xmlpath="drivers"/>
            <platform XML_version="1.2" id="platform_0">
                <instance XML_version="1.2" desc="DSK6713_0" href="boards/dsk6713.xml" id="DSK6713_0" xml="dsk6713.xml" xmlpath="boards"/>
            <board XML_version="1.2" description="Spectrum Digital C6713 DSK Board" id="DSK6713_0">
                    <cpu HW_revision="1.0" XML_version="1.2" description="C671x CPU" deviceSim="false" id="TMS320C671X" isa="TMS320C671X">
                        <property Type="choicelist" Value="0" id="bypass"/>
                    </cpu>
                </board>
                <instance XML_version="1.2" desc="TMS320C2812_0" href="devices/c2812.xml" id="TMS320C2812_0" xml="c2812.xml" xmlpath="devices"/>
                <instance XML_version="1.2" desc="TMS320C2812_1" href="devices/c2812.xml" id="TMS320C2812_1" xml="c2812.xml" xmlpath="devices"/>
                <device HW_revision="1" XML_version="1.2" description="" id="TMS320C2812_1" partnum="TMS320C2812" simulation="no">
                    <cpu HW_revision="1.0" XML_version="1.2" desc="C28xx_0" description="CPU" deviceSim="false" id="C2800" isa="TMS320C28XX">
                        <property Type="choicelist" Value="0" id="bypass"/>
                    <property Type="filepathfield" Value="..\..\emulation\gel\f2812.gel" id="GEL File"/>
                    <property Type="choicelist" Value="1" id="Slave Processor"/>
                    </cpu>
                </device>
                <device HW_revision="1" XML_version="1.2" desc="TMS320C2812_0" description="" id="TMS320C2812_0" partnum="TMS320C2812" simulation="no">
                    <cpu HW_revision="1.0" XML_version="1.2" description="CPU" deviceSim="false" id="C2800" isa="TMS320C28XX">
                        <property Type="choicelist" Value="0" id="bypass"/>
                    <property Type="filepathfield" Value="..\..\emulation\gel\f2812.gel" id="GEL File"/>
                    <property Type="choicelist" Value="1" id="Slave Processor"/>
                    </cpu>
                </device>
            </platform>
        </connection>
    </configuration>
</configurations>

0 Ricky Lau over 8 years ago in reply to Jens Biltoft

TI__Genius 11435 points

Jens,

Can you try the updated ccxml file? Specifically, I changed the C2812 cores to be F2812, which are the flash versions of C2812. So hopefully, you will now be able to program the flash on these cores.

Thanks,

Ricky

C6713.ccxml

0 Jens Biltoft over 8 years ago in reply to Ricky Lau

Expert 1220 points

Thanks Ricky
That solved the problem.
I will now move on with the migration, now that I am able to run the code on the debugger.
Best
Jens

C2000™︎ microcontrollers

C2000 microcontrollers forum

Can't initialize external memory interface on TMS320F2812