F28069 ADC by near ADC channels disturbance

Hi Devin,

Thanks for your answers, very grateful.

I did some labs and can solve for this issue.
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1. Sampling B1 in a row.
2. Increase the S+H duration ( ACQPS = 0x20; from 0x06)
3. Add a 100nF cap, but affect response delay.

best regards,
Simen

Devin,

The problem is still there even we sample B1 twice in a row, the second sample affected by B0 input voltage. Finally, we fix this problem by changing the channel sampling order to B0, A7 and then back to B1. This means that we have to sample one ADC channel on another S/H and then back to B1 to avoid this problem.

We wonder how this could happen, please advise your idea on this situation, thanks in advance.

Luke

Hi Luke,

I think this is expected based on the input impedance of your signal.  You should add an op-amp to drive the signal, increase the S+H duration to an appropriate time (if possible), or add a capacitor on the pin that is at least 4096 * 4 * (5pF + 1.6pF) = ~100nF.  Note that with the 100nF capacitor, you will have a sample rate limitation given by the external resistor : if you sample too fast, charge will slowly bleed off of the external cap.  

Here is a settling simulation in TINA for ACQPS = 6, Rin = 1.04k, Cin = 100pF.  You can see there is significant settling error:

Note that 100pF external capacitance was arbitrarily chosen; with a smaller external capacitance settling should be much better.  

Here is the TINA simulation file if you wan to try this yourself:

Piccolo_impedance_settling.TSC

Edit: Note that in the simulation, you are ideally trying to get the settling to 1/4th of an LSB or better = (1/4096)*(1/4)*3.3V = 0.2mV.

Hi Devin,

For evaluation, we use DC power source providing DC voltage on B0, no other components are connected.

We get same result and must sample B0 first, switch to A7 and back to B1 then get correct results, increasing S+H duration doesn't work, is this reasonable? My customer is wondering what's the reason we can avoid crosstalk if switching ADC channel to A7(another S/H), could you advise your idea please?

Your help is appreciated, thanks.

Luke

Hi Luke,

Is the signal buffered locally before going to the voltage divider? Even though a power supply has a low resistance output, the cable inductance can cause inadequate settling. You can try adding a large capacitance at the end of the cable to mitigate the inductance.

Can you simulate your circuit and determine what an appropriate S+H duration is? Is it even possible to select an appropriate S+H duration given the input impedance?

Hi Devin,

Thanks for your response and suggestion.

Do you have idea why we can avoid this problem if switch to A7 first before scampling B1?

Luke

This is because some residual charge is left on the ADC S+H capacitor after each sample, correlated to whatever voltage was sampled. With A7 in-between, the cap starts at some other value and so you see some different behavior.

Can you give me the resistance, capacitance, and S+H duration for B0, B1, and A7?

Devin,

The picture below is the schematic and IMPPT1-D is connected to ADC B1. My customer has another test on this problem, they set all the 16 SOC doing B1 sampling, use scope to measure the voltages of test points IPV1 and IMPPT1-D and gets the results below,

• IPV1 = 167mV.
• IMPPT1-D = 236mV.

They do nothing but sampling B1 and measure the voltages of the points. Why can they get that IMPPT1-D voltage even higher than the voltage of IPV1? Is it possible ADC B1 outputs voltage?

This project is almost in production, need your help to fix and convince the customer to use F28069 without any concerns. Please advise your idea, thanks.

Luke

Hi Luke,

Ok, yeah we can explain the behavior here.  The effective source impedance is extremely high.  Since you have a 3-pole filter here, just as a really rough approximation we can say that the total RC time constant is roughly sqrt(RC1^2 + RC2^2 + RC3^2) = sqrt(57.6K*100n^2+ 57.6K*100n^2 + 1K*1n^2) = 8.15ms. To get 1/4LSB settling at 12-bit resolution, you need -ln(0.25/4096) = 9.7 time constants, so for ideal settling your S+H window would need to be in the ballpark of 8.15ms*9.7 = 79.1ms!  The maximum S+H window for the ADC runing at 30MHz is 64 ADCCLKs or (1000/30)*64 = 2.1us.

Now, if you don't want to sample at full speed, you can place a very large capacitance on the ADC input.  This usually needs to be at least 4096*4*internal ADC capacitance.  If you look at the input model we provide in the datasheet here:

You would need at least (5pF+1.6pF)*4096*4 = 108.1nF.  This needs to be directly on the ADC pin so that this capacitor can provide all the charge for the ADC internal S+H capacitor.  In this case you can use the minimum S+H window, but the maximum sample rate is reduced.  The sample rate is reduced because the ADC can effectively source a small amount of current out of the pin when the internal capacitance equalizes with the external capacitance.  The external source impedance is still very high, so instead of trying to charge the internal S+H capacitor during the S+H phase, you are now trying to re-charge the external capacitance in the time between samples.  If the external RC is large (which it will be with a large external capacitance) you need to wait a long time for the external C to recharge, otherwise you will slowly cause the external C to drift with each sample (this is what you are seeing).  

Here is a simulation of what you are seeing on the pin.  The ADC samples at 1MSPS.  Even though a perfect source is driving towards 0V, the pin voltage eventually rises to almost 1.5V after about 50ms.  This is because the conversion process leaves a residual voltage of 3.3V on the ADC internal capacitors and the external source can't overpower this due to extremely high source impedance.  Note that the residual voltage usually won't be this high, but it is best to simulate worst possible case: either a maximum possible input,  3.3V in this case, with the internal capacitance always completely discharged, or (to demonstrate that the pin voltage can also rise) a 0V source with a 3.3V residual voltage.

Now decreasing the sample rate to 10KSPS, you can see that the situation has improved, but still isn't great (~40mV of drift):  

Now at 100SPS the capacitor completely recovers to within <1LSBs:

Here is the TINA file if you want to simulate this yourself:

PiccoloSampleRate_settling.TSC

Now as to what the customer should do:

With the current circuit, they would need to sample at no more than 100SPS.  A better solution would probably be to replace the two 57.6k resistors with 0-ohm, de-populate the two 100nF caps, and then have the final RC be 50ohms and 10pF.  

Note that with a small R and a huge C, it is possible to create a very low pass filter that the ADC can over-sample.  If we turn the filter above into a single-pole filter, with R = 50ohms and C = 10uF, you get a pole at about 318Hz and the ADC can sample this at 100KHz:

If you need a 3-pole filter, you can probably do something similar where you select the R for each stage to be ~15 ohms and use a huge C.  Warning: this strategy is transferring the design challenges up the chain to the op-amp; it can be challenging to ensure that the op-amp can drive such a huge capacitive load without becoming unstable and oscillating.   

Devin,

Wow, what a detailed description. You do help us a lot.

One more question here. Conversion process leaves a residual voltage of 3.3V on the ADC internal capacitors and according to your simulation, when ADC samples at 1MSPS with a 0V source, the pin voltage rises to 1.5V finally.

So, do you mean the residual voltage may come from both external and internal power source? Where does that internal residual voltage come from please?

Your support is really appreciated, thank you.

Luke

Hi Luke,

The internal capacitors have some voltage left on them from the conversion process. This voltage should be between the VREFHI and VREFLO voltages of the ADC. The charge on the capacitors comes from some combination of the last voltage sampled, and the VREFHI and VREFLO voltages of the ADC. Usually it is somewhat near the voltage that was converted last in the sequence, but this can vary depending on the architecture, so it is best to assume that it could be either 0V (VREFLO) or VREFHI.

Dear Devin,

Above reply says that the internal capacitors may affect by conversion process between VERFHI and VERFLO.
Could you give more detail information about this situation?
Because it is a continuous noise source to disturb ADC.
And how to build a simulation model for them?
(according to Custom' result: HW Voltage source IPV = 167mV, MCU ADC Pin = 236mV --> Why the MCU ADC Pin higher about +69mV)

best regards,
Simen

Hi Simen,

This is a fundamental issue in all ADCs.  The S+H is capacitive in nature, and the external signal source needs to be strong enough to charge/discharge it to the target voltage during the sampling time.  What is left on the capacitor depends on the specific architecture, so the best was to treat this is to assume the worst case: that the capacitor could be fully discharged/charged from the previous sample and conversion. 

The models are provided above to simulate this.  You need to ensure that either (1) The external source can completely charge/discharge the internal S+H capacitance to within 1/4 LSBs or better during the S+H phase.  This can controlled by lowering the source impedance and/or increasing the S+H duration.  (2) Instead, the external capacitance directly on the pin is made to be at least as large as (internal cap * 2^(N+2)), where N is the ADC resolution (or desired resolution if you are OK with less).  In this case, simulation should be done to ensure that the external capacitance recovers to within the desired resolution over time for a given sample rate.  This can be controlled by reducing the sample rate and/or reducing the impedance driving the large capacitance on the pin.  

Hello Devin,

Thanks for your help, this customer knows that ADC source impedance will affect the conversion result now.

Regarding the ADC pin output certain voltage level versus sampling rate, I believe that this is about the ADC hardware architecture and is not so easy to have a detailed description here, but this customer doesn’t buy in and is asking for further, detailed information.

Please help to advise your idea, how can this customer get the detailed information he needs? Can he contacts you via email for further discussion if needed please?


Luke

Hi Luke,

I think you have everything you need to convince them.  The model of the ADC is in the thread above.  The charge coming out of the ADC is well understood and applicable to all ADCs.  You can see this in various TI app notes here:

http://www.ti.com/lit/ml/slyp166/slyp166.pdf

http://www.ti.com/lit/an/spna061/spna061.pdf 

"If the source impedance is low enough, this effect is less than 1/2 LSB, so who cares. But as Rsource increases, more and more of the contaminated signal is allowed to accumulate on channel [N+1]’s external capacitor, Cext[N+1]. With each conversion loop, Cext[N+1] is booted (up or down) by a few microvolts that accumulate. Eventually channel [N+1] stabilizes with a new (but incorrect) value."

Dear Devin, 

we already know about your point about:
"This is a fundamental issue in all ADCs. The S+H is capacitive in nature, and the external signal source needs to be strong enough to charge/discharge it to the target voltage during the sampling time. "

The only point we want to know more detail is this picture (in red):

We can find an unexpect voltage signal when we only measure one ADC without any other ADC input.
We believe there's another source inside ADC module of DSP,can you provide more detail about this source?
hereinafter is our test method in detail:
(1)
 
  DSP Only sampling B1 channel (IPV ADC Pin)
  HW Voltage source IPV = 167mV, MCU ADC Pin = 236mV --> Why the MCU ADC Pin higher about +69mV
  
(2)
 According to the result of (1), this isn't cross talk. (DSP Only sampling B1 channel)
 

EE John & FW Jerry

Dear Devin, 

we already know about your point about:
"This is a fundamental issue in all ADCs. The S+H is capacitive in nature, and the external signal source needs to be strong enough to charge/discharge it to the target voltage during the sampling time. "

The only point we want to know more detail is this picture (in red):

 

 

We can find an unexpect voltage signal when we only measure one ADC without any other ADC input.
We believe there's another source inside ADC module of DSP,can you provide more detail about this source?
hereinafter is our test method in detail:
(1)
 
  DSP Only sampling B1 channel (IPV ADC Pin)
  HW Voltage source IPV = 167mV, MCU ADC Pin = 236mV --> Why the MCU ADC Pin higher about +69mV
  
(2)
 According to the result of (1), this isn't cross talk. (DSP Only sampling B1 channel)
 

EE John & FW Jerry

Jerry,

The picture that you posted is not showing up. Can you try to re-post the picture or describe the "red" behavior in words?

-Tommy

Tommy,

About the picture, pls. Refer to "page 12  in

The "red" part is DSP internal equivalent circuit.

Hi Jerry,

The voltage left on the capacitor isn't guaranteed to be whatever was sampled in from the previous sample.  Depending on the ADC architecture, the charge is redistributed, scaled, amplified, etc. in order to process the conversion. This could result in needing to discharge a voltage that is higher or lower than the previous sample (usually the voltage is close to the previous conversion, but you should never count on this property).  This is why we say that the ADC input driver needs to be strong enough and the S+H needs to be long enough to completely charge or discharge the S+H capacitor.  If it can charge/discharge a capacitor that is at the VREFHI or VREFLO rail (worst case) then it can handle whatever the actual voltage happens to be (which as previously mentioned is unpredictable).