• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 81 subscribers
  • Views 1909 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

F28069 shared analog input for ADC and Comparator

Stuart Baker
Genius 10330 points

I have a customer concerned about sharing a single input pin simultaneously between the ADC and Comparator input channel:

I have a quick and hopefully easy question about ADC and comparator input channels (COMP1A, etc.).  Is it possible to sample the same pin at the same time as an analog comparator input and ADC input channel, or does that cause something to not work correctly or sample with additional error, false trips, etc.?  For example, on the F28062 100-pin package, pin 21 is both COMP1A and ADCINA2.  The analog pin mux setting is the same for either purpose, so can I use that pin for both the comparator and sample it with the ADC at the same time?  We haven’t done this in the past, so I’m not sure what caveats there might be.

I  suggested that because of possible leakage, the ADC sampling time may need to be slightly larger for the ADC hold capacitor.  Our bigger concern however is that when charging the sample and hold capacitor, the voltage will drop on the comparator and cause a false trip.  I also suggested two separate input pins with a bulk capacitor on each.

Unfortunately right now all 16 ADC inputs are spoken for, with 2 of them being for the current transformer (CT) inputs to COMP1A and COMP2A.  A voltage drop to the comparator input channel wouldn’t be bad as long as there isn’t an overshoot at the end of the voltage drop period, as we are looking for increasing voltage spikes that indicate excessive input current draw.  Reading the analog CT signal levels by the ADC isn’t a requirement, so worst case we just wouldn’t do that.  The hardware guys want to ADC-sample the CTs also to act as a slow fuse besides doing the instantaneous trip.

I'm looking for additional guidance for allowing the comparator and ADC sampling to coexist on the same pin.

Thanks,

Stuart

  • 0
    TI__Guru 60865 points

    Hi Stuart,


    I think most times it should be possible to use the ADC and comparator at the same time on the same pin. 

    As you point out, there will be some disturbance to the pin voltage when the ADC samples.  You can actually simulate this using the input model we provide in the device datasheet:

    Note that Cp is after the device mux, and could be discharged between samples. 

    Here is a simulation of the pin voltage during a sample assuming that we are driving in 3.3V, the internal capacitors are completely discharged from the previous sample, and we have a low impedance and low capacitance source.  There is a significant transient voltage on the pin as the external and internal capacitances equalize, but the transient is narrow since there is a low impedance driving source:

    To deal with this, in the comparator we have some qualification logic:

    This can let you qualify the trip up to 16 SYSCLKs = 178ns.  In the case of the case of the fast transient, the input recovered in ~40ns, so this filtering should work well. 

    You also have the option of qualifying the trip inside the ePWM in the DC submodule. 

    Now if we increase C, we can actually deal with the transient from an analog perspective. The transient magnitude is decreased significantly (but the transient duration is increased, and we will need to increase the ADC S+H from the minimum to allow the input to settle):

    This still leaves some transient error, but you may be able to get the error to an acceptable level. 

    If you have a slower sample rate and lower analog bandwidth, I would recommend placing a capacitor that is at least (5pf+1.6pF)*4096*4 = 108nF on the pin.  This will provide all the charge for sampling, greatly reduce any pin transients, and allow the minimum S+H duration to be selected.  (If the source impedance is too high or the sample rate is too fast, the external capacitance won't recover between samples and the pin voltage will slowly drift.)  

    If we increase R from 50ohms to some other larger value, the transient duration will increase, which could be a problem. 

    Note that the transient could be in either direction - positive or negative - depending on what is left on the internal capacitors from the previous conversion process.  It is usually good to assume these could be the worst case: completely discharged if you are trying to drive a voltage > VREFHI / 2, or completely charged if you are trying to drive a voltage < VREFHI / 2. 

    Also attached is the TINA model here if you want to simulate yourself:Piccolo_InputTransient.TSC

  • 0
    TI__Guru 62975 points

    Stuart,

    There is also hysteresis implemented on the comparators similar to this picture from Wikipedia:

     

    The collective R1 + R2 feedback resistance is roughly 100kΩ.  That can be included in any modeling exercise that is planned.

    -Tommy