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TMS320F28069: eQEP interrupts not functioning correctly when SCI is enabled

James Holley99
Prodigy 60 points
Part Number: TMS320F28069

I have implemented motor control code that uses the eQEP to interrupt every time a pulse is registered.  This is important to my application, as no interrupt can be missed in order to successfully commutate the motor.  I have added SCI in order to send commands to the microcontroller.  The motor spins as expected, but when I send commands via SCI to the driver, I start to miss pulses which eventually causes the motor to stop spinning.  I think this is because reading from the SCI buffer is causing me to miss eQEP interrupts, but I'm not exactly sure how to test this.  Below are my register settings for the eQEP and SCI.  Any help on this is much appreciated!

SciaRegs.SCIFFTX.all=0xE040;
SciaRegs.SCIFFRX.all=0x2044;
SciaRegs.SCIFFCT.all=0x0;

SciaRegs.SCICCR.all =0x0007; 
SciaRegs.SCICTL1.all =0x0003; 

SciaRegs.SCICTL2.bit.TXINTENA =1;
SciaRegs.SCICTL2.bit.RXBKINTENA =1;

SciaRegs.SCIHBAUD =0x0000;
SciaRegs.SCILBAUD =0x0002;
SciaRegs.SCICTL1.all =0x0023; 

EQep1Regs.QUPRD=18000000; 
EQep1Regs.QEINT.bit.PCO = 1; 
EQep1Regs.QEINT.bit.PCM = 1; 
EQep1Regs.QEPCTL.bit.FREE_SOFT=2;
EQep1Regs.QEPCTL.bit.PCRM=1; 
EQep1Regs.QEPCTL.bit.UTE=0; 
EQep1Regs.QEPCTL.bit.QCLM=0; 
EQep1Regs.QPOSMAX=0x00000800; 
EQep1Regs.QPOSCMP=0x00000000; 
EQep1Regs.QEPCTL.bit.QPEN=1; 
EQep1Regs.QCAPCTL.bit.UPPS=1; 
EQep1Regs.QCAPCTL.bit.CCPS=2; 
EQep1Regs.QCAPCTL.bit.CEN=1; 
EQep1Regs.QPOSCTL.bit.PCE = 1; 

  • 0
    TI__Guru 57255 points

    Hi James,

    It appears that you are using ISRs for both the SCI and QEP.  Note that, by default, the CPU does not enable the nesting of interrupts.  This means that a QEP interrupt may have to wait until the SCI interrupt code is complete before it is able to begin.

    Assuming this is the root cause, there are a few paths you could take to resolve this:
    1) Reduce the size of your SCI interrupt.  This will help things, but potentially not enough.
    [ie just read the buffer into variables in the interrupt; parse and process the data outside the interrupt]
    2) Enable interrupt nesting if your SCI interrupt needs to be sufficiently long.  Please see:
    http://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x
    3) Take the SCI receive/transmit software out of interrupts.  Instead check for SCI event flags within your 'while' loop at the end of main (flag polling).  If done this way, you will then only have one interrupt (the QEP) and therefore will be able to dispatch your commutation code as soon as possible.  This is the lowest jitter solution.

    Hopefully this helps!


    Thank you,
    Brett

  • 0 in reply to Brett Larimore
    Prodigy 60 points
    Thanks for the heads up - I've found the culprit!

    I disabled SCI interrupts and found that the transmission time of the SCI was taking longer than a loop rate I had set on the CPU timer causing that interrupt to preempt the eQEP interrupt. I think some form of the nested interrupts you listed above is the correct action. Thanks for bringing up these options!