CCS/TMS320F28379D: ADC Sampling rate issue

Thank you for your reply Gautam. Can you help me in how to change the TBPRD value to get 44.1 kHz. I'm very new to CCS and tidsp. 

Thank you.

Best regards,

Sainath Reddy. 

Hi Sainath,

Conceptually, the longer the ePWM period the slower the sample rate. Some of the factors that affect the ePWM period:

*Pll settings / actual CPU speed
*SYSCLK to ePWM global clock divider (in ClkCfgRegs.PERCLKDIVSEL register)
*ePWM time-base pre-scaler
*TBPRD value
*Up-count mode or up-down count mode

Also event pre-scalers might affect the trigger frequency (i.e. if you only generate one trigger every Nth compare or period match event)

Since there are many factors here, I'd recommend that you configure the ePWM to toggle a pin on the same event that generates the trigger. This will let you verify the triggering frequency using an oscilloscope.

Some mostly minimal code to get an ePWM onto the pin is in this thread:
e2e.ti.com/.../634282

Thank you for your reply Devin. I calculated TBPRD value as TMPRD = 200 MHz / 44.1 kHz = 4308. 

Is it the right way to calculate the TBPRD value. If it is correct, do I need to give the value directly as 4308 or do I need to convert in to hex.

Do I need to change any other register values to change the sampling rate???

Another issue that I am facing with the ADC is that the digitized output. Does it generally occur becaue of any error in my code. 

Thank you.

Regards,

Sainath Reddy.

Hi Sainath,

That is the general idea of how you want to compute the period, but the result will not be correct.

The effective ePWM clock, due to the global divider in the ClkCfgRegs.PERCLKDIVSEL register will likely be 100MHz (but go check the contents of that register and read about what the register does in the TRM).

The ePWM TBPRD also can have a local clock divider for the module, so you need to check that value too.

It is also worth checking the pll input clock (X1 pin) and the pll multiplier and divider settings to ensure that the 200MHz system clock is correct.

Overall, since there are many possible settings that could change the timings, you will want to get the ePWM to toggle a pin so you can verify timings with a scope (or alternately you can input a waveform to the ADC of known frequency and then examine the converted results).

Yes, you can just write the 4308 (or whatever you come up with) directly to the TBPRD register as an integer. hex values have a leading '0x'. e.g. 0x10D4.

I'm not sure I follow your problem with ADC results? Is the digital value off from expectation by more than the tolerances specified in the datasheet for the module performance?

Basically, I am giving a sine wave input through a function generator to the ADC of the TI DSP. So, when I am verifying the ADC output. But, the ADC output pattern is distorted at some portions. Do you know why these error in the output generally occur. Is it because of error in the code or any other reason.

Thank you.

Regards,

Sainath Reddy.

Hi Sainath,

This distortion could be for a variety of reasons.  Some of these could be:

• Signal delivery to the ADC is not good due to cabling, impedance mis-match, or inadequate drive strength or bandwidth.   
  • Ideally you would use a short shielded cable like a BNC cable and then locally buffer the signal on the board with a high-bandwidth and low noise op-amp.  The op-amp output to the ADC input should have a low R value (maybe 30 to 50 ohms) and a capacitor on the ADC input of 10x to 20x Ch.

Inadequate S+H time.

• If the input has a high impedance, you need to increase the S+H duration (controlled by the ACQPS setting).  This can also include the inductive impedance of cabling between your function generator and the ADC input (which is why, ideally, you would buffer the input locally on the board near the ADC input).

Issues with the ADC support circuits or basic settings

• If the ADC clock is higher than the max rating specified by the datasheet, the output could be distorted or just garbage
• If the VREFHI input is not stable and driven by a good source, distortion could occur.  Note that a revision of one of the F2837x ControlCard has an erratum related to the buffer capacitors on the VREFHI input.
• if the VDDA power supply is out of range or current limited, the ADC could produce distorted outputs

• Sampling rate issues could cause aliasing that make the sampled waveform something unexpected. Usually this would be if the sample rate is too slow though.