Other Parts Discussed in Thread: C2000WARE, CONTROLSUITE
Tool/software: Code Composer Studio
I am having issues connecting the EMIF of F28379D to Xilinx FPGA.
This is my async emif1 function
void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel)
{
Uint16 i;
// data pins XD0-15
for (i=69; i<=85; i++)
{
if (i != 84)
{
GPIO_SetupPinMux(i,cpu_sel,2);
}
}
//address pins XA0-15
for (i=38; i<=52; i++)
{
if ((i != 42) && (i != 43))
{
GPIO_SetupPinMux(i,cpu_sel,2);
}
}
for (i=86; i<=88; i++)
{
GPIO_SetupPinMux(i,cpu_sel,2);
}
GPIO_SetupPinMux(31,cpu_sel,2); // EM1WEn
//GPIO_SetupPinMux(33,cpu_sel,2); // EM1R/nW
GPIO_SetupPinMux(34,cpu_sel,2); // EM1CS2n
//GPIO_SetupPinMux(36,cpu_sel,2); // EM1WAIT
GPIO_SetupPinMux(37,cpu_sel,2); // EM1OEn
GPIO_SetupPinMux(30,cpu_sel,2); // EM1CLK
//GPIO_SetupPinMux(88,cpu_sel,3);
GPIO_SetupPinMux(89,cpu_sel,3);
GPIO_SetupPinMux(90,cpu_sel,3);
GPIO_SetupPinMux(91,cpu_sel,3);
GPIO_SetupPinMux(92,cpu_sel,3);
GPIO_SetupPinMux(93,cpu_sel,3);
GPIO_SetupPinMux(94,cpu_sel,2);
//setup async mode and enable pull-ups for Data pins
//
for (i=69; i<=85; i++)
{
if (i != 84)
{
GPIO_SetupPinOptions(i,0,0x31); // GPIO_ASYNC||GPIO_PULLUP
}
}
}
My main is as follow:
void main(void)
{
long *DUTY;
setup_emif1_pinmux_async_16bit(1);
// Initialize system control
InitSysCtrl();
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xS_PieCtrl.c file.
//
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
EALLOW;
IER = 0x0000;
IFR = 0x0000;
EDIS;
// Initialize the PIE vector table with pointers to the shell Interrupt
// GService Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2837xS_DefaultIsr.c.
// This function is found in F2837xS_PieVect.c.
InitPieVectTable();
//Configure to run EMIF1 on full Rate (EMIF1CLK = CPU1SYSCLK)
EALLOW;
ClkCfgRegs.PERCLKDIVSEL.bit.EMIF1CLKDIV = 0x0;
EDIS;
EALLOW;
// Grab EMIF1 For CPU1
Emif1ConfigRegs.EMIF1MSEL.all = 0x93A5CE71;
//Disable Access Protection (CPU_FETCH/CPU_WR/DMA_WR)
Emif1ConfigRegs.EMIF1ACCPROT0.all = 0x0;
// Commit the configuration related to protection. Till this bit remains set
// content of EMIF1ACCPROT0 register can't be changed.
Emif1ConfigRegs.EMIF1COMMIT.all = 0x1;
// Lock the configuration so that EMIF1COMMIT register can't be
// changed any more.
Emif1ConfigRegs.EMIF1LOCK.all = 0x1;
EDIS;
Emif1Initialize();
//Configure the access timing for CS2 space
Emif1Regs.ASYNC_CS2_CR.all = ( EMIF_ASYNC_ASIZE_16 | // 16Bit Memory Interface
EMIF_ASYNC_TA_1 | // Turn Around time of 2 Emif Clock
EMIF_ASYNC_RHOLD_1 | // Read Hold time of 1 Emif Clock
EMIF_ASYNC_RSTROBE_4 | // Read Strobe time of 4 Emif Clock
EMIF_ASYNC_RSETUP_1 | // Read Setup time of 1 Emif Clock
EMIF_ASYNC_WHOLD_1 | // Write Hold time of 1 Emif Clock
EMIF_ASYNC_WSTROBE_4 | // Write Strobe time of 1 Emif Clock
EMIF_ASYNC_WSETUP_1 | // Write Setup time of 1 Emif Clock
EMIF_ASYNC_EW_DISABLE | // Extended Wait Disable.
EMIF_ASYNC_SS_DISABLE // Strobe Select Mode Disable.
);
DUTY = (long *)CS2_START_ADDRESS;
*DUTY = 0x35;
while (1);
}
when I run it and look at memory address 0x10 0000, all I see is 1000 regardless of the data. I tried to CS2n pin to FPGA to see if I had loading issues but it hasnt worked.
Thank you kindly in advance.