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TMS320F280049: incorrect information for the description of ADCINTFLGCLR register

Aki Li
Expert 8845 points
Part Number: TMS320F280049

In the TRM, there might be sth wrong for the description of ADCINTFLGCLR register. Could you help check which one is the right one? 


0 No action
1 Clears respective flag bit in the ADCINTFLG register. If software
sets the clear bit on the same cycle that hardware is trying to set the
flag bit, then hardware has priority but the overflow bit will not be
affected (retains current state)
Boundary condition: If hardware is trying to set the bit flag while
software tries to clear the bit in the same cycle, the following will take
place:
1. SW has prioirity and will clear the flag
2. HW set will be discarded
no signal will propagate to the PIE from the latch
3. Overflow flag/condition will be generated

  • 0
    TI__Mastermind 30685 points

    Hi Aki,

    I think what you are suggesting is to replace the numbered item list pertaining to the events in the Boundary condition: If hardware is trying to set the bit flag while software tries to clear the bit in the same cycle, the following will take
    place:

    a. SW has prioirity and will clear the flag

    b. HW set will be discarded no signal will propagate to the PIE from the latch

    c. Overflow flag/condition will be generated

    The numbered list may be confused as the value of ADCINTFLGCLR (as this bit will only have a value of either a '0' or '1').  Can you confirm?  We can change the description by removing the numbered list to avoid confusion.

    Best regards,

    Joseph

  • 0 in reply to Joseph Casuga
    TI__Expert 8845 points

    Joseph,

    No, I found the description for Bit set to 1 is in contrast to the Boundary condition. One is that hardware has priority, while the the Boundary condition said SW has priority.

  • 0 in reply to Aki Li
    TI__Mastermind 30685 points

    Hi Aki,

    You are correct.  The statement "If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority but the overflow bit will not be affected (retains current state)" is contradicting the boundary condition.  The correct sequence of events is the one described in the boundary condition.  We filed this as a bug and it should be corrected in the next revision of the TRM.

    Thanks and regards,

    Joseph