DRV2700: Large output ripple and noise when driving a piezo actuator

Hi, Andy,

Welcome to E2E and thank you for your interest in our products!

We will take a look at this and will answer as soon as possible.

Best regards,
Luis Fernando Rodríguez S.

Hi, Andy,

I found a similar issue in this E2E thread:

https://e2e.ti.com/support/motor-drivers/f/38/t/683015?tisearch=e2e-quicksearch&keymatch=drv2700evm-hv500%20noise

Could you try increasing the output capacitance? It must help to reduce the voltage ripple as stated in page 25 note.

Please let me know if you have additional observations on this.

Best regards,
Luis Fernando Rodríguez S.

Andy,

Do you have a feedback on this?

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

Thank you kindly for the fast reply, and sorry I've been out.

I tried adding 0.47uF across the load and it made a huge difference -- the 20-30VPP "glitches" have been largely eliminated:

CH1 (yellow) is DC output, CH2 (blue) is input. 

However there is still some "burst" noise at ~40VDC output that I am trying to clean up.

As you can see below, I am getting this 3VPP noise at 40VDC output:

CH1 (yellow) is DC output, CH3 (purple) is AC noise at the output. 

In the 40ms view at the top you can see that I am getting 2-3VPP triangle wave output at about 25Hz,

and as you can see below it again aligns with the transistor in the flyback network:

CH1 (yellow) is DC output, CH2 (blue) is Q1 gate, CH3 (purple) is AC output noise.

I've experimented with a range of cap values at the output.  How can I further reduce the output noise?  Since the noise aligns with the transistor, will tuning the caps in the feedback network impact the output noise?

Also, the DRV2700EVM does not include a transistor Q1 -- would I get better results by eliminating the flyback circuit and this transistor, though it is limited to 105V output?

Thanks very much,

Andy

Hi Luis,

I tried removing the piezo actuator form the circuit and connecting only the 0.47uF capacitor across the output of the DRV2700EVM-HV500 module, and I get exactly the same noise signature mentioned in my previous post.  So it seems that this behavior should be reproducible with no mods to the eval board, both switches set to HIGH, and a generic 0.47uF ceramic cap across the output.  Are you able to reproduce this behavior?  

Because the 2VPP noise is at such a low frequency, 20-40Hz, it unfortunately is quite audible in our mechanical setup -- it vibrates the piezo and the mirror that is attached to it.  And 105V output only gives us 2/3 of the piezo displacement, which may be too little for our application.  But I will order a 105V eval board and test it as a troubleshooting step.

I agree that using as little output capacitance as possible is best to avoid limiting bandwidth so I've ordered 0.1uF 500V caps that will arrive tomorrow to test.  Perhaps I can reduce the capacitance at the output and still eliminate the very large 30VPP spikes.

Thank you,

Andy

Hi, Andy,

I was able to reproduce this behavior and effectively I got large spikes of around 39Vpp with no load connected.

I tested different capacitors at the output and they helped to reduce significantly the output spikes.

Using a capacitor value of 10nF reduced the spikes to 9Vpp.

Using a capacitor value of 1uF reduced the spikes to 1.2Vpp.

Unfortunately, I couldn't test the EVM performance with the C6 capacitor connected (the EVM schematic suggests a 0.047uF, 630V, X7R capacitor). I don't have a capacitor with these characteristics (or similar). Do you have a capacitor like this? It could be useful to improve the signal performance of this EVM.

http://www.ti.com/lit/ug/slou407a/slou407a.pdf#page=20

I tested the EVM with no flyback connection and there are no spikes at the output. So, it could be an alternative.

Please let me know if you have additional observations on this.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

Thanks very much for testing this. 

I do have a 0.047uF cap and I soldered it to the C6 pads on my EVM-HV500 board.  It gets rid of the large 39Vpp spikes as you mentioned, but 1-2Vpp spikes remain, particularly at an output voltage of around 40VDC.  I think the performance is slightly better at 0.1uF cap across the output.  I also tried additional caps of 100pF, 1,000pF, and 10,000pF all in parallel and in addition to the 0.1uF cap with no apparent effect.  I am not seeing additional benefit from tweaking the output capacitance.

Do you have any recommendations for adjusting feedback capacitance that may also have an impact, C13, C18, C19, C21?  I would expect these would affect the VGate node and lead to positive feedback if not tuned correctly.  

Thank you,

Andy

Hi, Andy,

Sorry for my late reply.

I wouldn't recommend to modify these values since it may affect the performance of the device. Regarding the measurements and captures that you have made, are these from the differential output or just from OUT+ or OUT-? If the ripple still seen the differential signal? I mean, as mentioned in the datasheet, the ripple should be removed in differential mode.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

Can the flyback converter be configured for differential output?  The schematic for the DRV700EV-HV500 shows has 1 of the 2 pins on the output connector, J2, tied directly to GND, so I'm not sure how this would be connected for differential output.  If it can, please let me know how the circuit should be modified for differential output.

Thank you,

Andy

Hi, Andy,

I apologize for the confusion. I made a mistake. The flyback configuration doesn't have differential configuration.

I think that the best option here would be to try and evaluate the non-flyback version. Definitely it will not reach high voltages like the flyback version, but it should be enough to evaluate voltages around 100V and the ripple won't be an issue.

Best regards,
Luis Fernando Rodríguez S.