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Part Number: DRV8702D-Q1
I have a design composed of an Hbridge of CSD18540Q5B, a DRV8702-Q1 and an output filter. The output of the system is supposed to be a sinusoidal voltage from a PWM signal. With no load the system works perfectly, but with a load of let's say 10 ohms, the output voltage drops and the calculated impedance of the amplifier is approx 0.6 Ohm.
Here's a capture of the schematic (half of the bridge)
The inductor used is SRP1770TA-101M, the filter capacitor is PCV1K150MCL1GS and the free wheeling diode is V8PAM10HM3/I.
Can you recognise anything inherently wrong in the design?
Can you share a scope capture of what you are seeing to study it and indicate the the drop that troubles you?
A scope capture of OUT..., GH1, SH1, and GL1 will suffice. Thank you.
Hector HernandezMotor Applications Team
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In reply to Hector Hernandez Luque:
Thanks for sharing this information with me.
Here are the scope captures shared to me from you and your comments:
In here the captures you asked me. For all the images, the output is set at 10 Vdc and the bus voltage is 30 V.
With an 8Ohm load
Response from Hector -> "Question for you: what am I suppose to be seen on OUT1? The drop I see can be expected. Is it a problem that the OUT1 drops around 1 V? Also, the scope shots look very similar. Please, confirm that the load was connected on the third/fourth scope captures."
The scopes should be righties, there is no much difference between them; what I notice is a slight change in the on time when I connect the load vs without load.
I attach you also the scopes of GH1 and GH2. I find it curious that these two signals only change between unloaded and loaded when GH1 is rising and GH2 descending; when GH1 descends and GH2 rises there is no significant difference between loaded and unloaded.
The behavior of the output voltage dip is expected behavior. Can you explain how this dip is an issue for you?
As for the output change when the load is added, the load introduces resistance and inductance to the H-bridge, the gate signal slew rate is decreasing due to the added load.
I know it's expected, but it's higher that what I need as I'm using open loop control and I'd like to have somewhat repeatable results (+-2% approx) for different loads.
I took the evaluation board of the DRV8702-Q1 and measured the voltage on the top gates with and without load.
Now with my board:
I don't quite understand the cause of the difference in the shapes. the difference of the evaluation board and my board is mine has an output filter and a boost converter to generate the 30 V (the bus itself seems very stable). For the EVM, I generated the 30 V using a lab power supply.
In reply to Federico Silva:
Have you tried your board without the output filter? Thanks.
I've just removed the filter and the problems disappears, the board responds just as the EVM. Do you know why the filter add such an effect?
The inductance resistance is not that big and the capacitor I chose is a aluminium polymer capacitor, which has theoretically a good frequency response, the DC voltage bias is right and the ESR is low. The overall cuttoff frequency is 4 kHz, while the switching frequency is 25 kHz.
Do you have any suggestion to avoid this issue?
Please, expect a response by EOD Friday.
I am still investigating this question. I aim to have a response by EOD Tuesday.
The filter capacitors slow down the slew of the output, hence why you can see a slower slew on the gate signals that were probed.
Thanks for the response.
If that's the case, changing the transistors for faster ones (ie less Qg) and/or using a gate driver with more driving force should aid to avoid the issue, right?
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