Part Number: DRV8702D-Q1
I have a design composed of an Hbridge of CSD18540Q5B, a DRV8702-Q1 and an output filter. The output of the system is supposed to be a sinusoidal voltage from a PWM signal. With no load the system works perfectly, but with a load of let's say 10 ohms, the output voltage drops and the calculated impedance of the amplifier is approx 0.6 Ohm.
Here's a capture of the schematic (half of the bridge)
The inductor used is SRP1770TA-101M, the filter capacitor is PCV1K150MCL1GS and the free wheeling diode is V8PAM10HM3/I.
Can you recognise anything inherently wrong in the design?
Can you share a scope capture of what you are seeing to study it and indicate the the drop that troubles you?
A scope capture of OUT..., GH1, SH1, and GL1 will suffice. Thank you.
Hector HernandezMotor Applications Team
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Hector Hernandez Luque:
Thanks for sharing this information with me.
Here are the scope captures shared to me from you and your comments:
In here the captures you asked me. For all the images, the output is set at 10 Vdc and the bus voltage is 30 V.
With an 8Ohm load
Response from Hector -> "Question for you: what am I suppose to be seen on OUT1? The drop I see can be expected. Is it a problem that the OUT1 drops around 1 V? Also, the scope shots look very similar. Please, confirm that the load was connected on the third/fourth scope captures."
The scopes should be righties, there is no much difference between them; what I notice is a slight change in the on time when I connect the load vs without load.
I attach you also the scopes of GH1 and GH2. I find it curious that these two signals only change between unloaded and loaded when GH1 is rising and GH2 descending; when GH1 descends and GH2 rises there is no significant difference between loaded and unloaded.
The behavior of the output voltage dip is expected behavior. Can you explain how this dip is an issue for you?
As for the output change when the load is added, the load introduces resistance and inductance to the H-bridge, the gate signal slew rate is decreasing due to the added load.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.